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AM186ED Datasheet(PDF) 79 Page - Advanced Micro Devices |
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AM186ED Datasheet(HTML) 79 Page - Advanced Micro Devices |
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79 / 88 page  Am186ED/EDLV Microcontrollers 79 PRELI M INARY D RA F T SWITCHING CHARACTERISTICS over COMMERCIAL and INDUSTRIAL operating ranges Clock (20 MHz and 25 MHz) Notes: All timing parameters are measured at 1.5 V with 50 pF loading on CLKOUTA, unless otherwise noted. All output test conditions are with CL =50 pF. For switching tests, VIL=0.45 V and VIH =2.4 V, except at X1 where VIH =VCC – 0.5 V. a The specifications for CLKIN are applicable to the normal PLL and CLKDIV2 modes. The PLL should be used for operations from 16.667 MHz to 40 MHz. For operations below 16.667 MHz, the CLKDIV2 mode should be used. Because the CLKDIV2 input frequency is two times the system frequency, the specifications for twice the frequency should be used for CLKDIV2 mode. For example, use the 20 MHz CLKIN specifications for 10 MHz operation. Parameter Preliminary Unit 20 MHz 25 MHz No. Symbol Description Min Max Min Max CLKIN Requirements 36 tCKIN X1 Period(a) 50 60 40 60 ns 37 tCLCK X1 Low Time (1.5 V)(a) 15 15 ns 38 tCHCK X1 High Time (1.5 V)(a) 15 15 ns 39 tCKHL X1 Fall Time (3.5 to 1.0 V)(a) 55 ns 40 tCKLH X1 Rise Time (1.0 to 3.5 V)(a) 55 ns CLKOUT Timing 42 tCLCL CLKOUTA Period 50 40 ns 43 tCLCH CLKOUTA Low Time (CL=50 pF) 0.5tCLCL–2=23 0.5tCLCL–2=18 ns 44 tCHCL CLKOUTA High Time (CL=50 pF) 0.5tCLCL–2=23 0.5tCLCL–2=18 ns 45 tCH1CH2 CLKOUTA Rise Time (1.0 to 3.5 V) 33 ns 46 tCL2CL1 CLKOUTA Fall Time (3.5 to 1.0 V) 33 ns 61 tLOCK Maximum PLL Lock Time 1 1 ms 69 tCICOA X1 to CLKOUTA Skew 15 15 ns 70 tCICOB X1 to CLKOUTB Skew 25 25 ns |
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