68HC705JB3 datasheet(62/134 Pages) FREESCALE

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GENERAL RELEASE SPECIFICATION

November 5, 1998

MOTOROLA

16-BIT TIMER

MC68HC05JB3

9-6

REV 1

TCMPE — Timer Input Capture Comparator Enable

1 =

Timer input capture comparator is selected.

0 =

Timer input capture comparator schmitt trigger is selected.

NOTE

When the comparator and VDD/2 reference are enabled, PB0 pin will automatically

becomes an input pin, irrespective of DDR setting. However, it is recommended to

set PB0 as an input ﬁrst (via DDR), before enabling the comparator. A read of PB0

will reﬂect the TCAP pin status, not the PB0 register bit.

The comparator uses the VDD/2 reference as the compare voltage, resulting in a

typical output as shown in Figure 9-8.

Switching off the VDD/2 voltage reference by clearing TCMPE=0 will further save

power when the MCU is in a low power mode.

Figure 9-7. TCAP Input Signal Conditioning

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

OIER

TCMPE

VREF2

VREF1

VREF0

OIE3

OIE2

OIE1

OIE0

$000E

reset:

00000000

–

MUX

PB0/

TCAP

Voltage

Reference

VREF

PB0 I/O

PORT LOGIC

TCMPE bit

VDD ÷ 2

Schmitt Trigger

Comparator

To edge select and

detect logic

Freescale Semiconductor, Inc.

For More Information On This Product,

Go to: www.freescale.com

68HC705JB3 Datasheet(PDF) 62 Page - Freescale Semiconductor, Inc

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