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68HC705JB3 Datasheet(PDF) 14 Page - Freescale Semiconductor, Inc |
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68HC705JB3 Datasheet(HTML) 14 Page - Freescale Semiconductor, Inc |
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14 / 134 page  GENERAL RELEASE SPECIFICATION November 5, 1998 MOTOROLA GENERAL DESCRIPTION MC68HC05JB3 1-2 REV 1 • Power-Saving STOP and WAIT Modes • Available in 20-pin PDIP, 20-pin SOIC, 28-pin PDIP, and 28-pin SOIC packages 1.2 MASK OPTIONS The following mask options are available: • External interrupt pins (IRQ, PA0 to PA3): [edge-triggered or edge-and-level-triggered] • Port A, port B, and port C pull-down/pull-up resistors: [connected or disconnected] • PA0-PA3 external interrupt capability: [enabled or disabled] • OSC, crystal/ceramic resonator startup delay: [4064 or 224 internal bus cycles] • Low Voltage Reset (LVR): [enabled or disabled] • COP function of MFT: [enabled or disabled] 1.3 MCU STRUCTURE Figure 1-1 shows the structure of MC68HC05JB3 MCU. Freescale Semiconductor, Inc. For More Information On This Product, Go to: www.freescale.com |
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