68HC705JB3 datasheet(63/134 Pages) FREESCALE

63 / 134 page

November 5, 1998

GENERAL RELEASE SPECIFICATION

MC68HC05JB3

16-BIT TIMER

MOTOROLA

REV 1

9-7

Figure 9-8. TCAP Input Comparator Output

When the input capture circuitry detects an active edge on the TCAP pin, it

latches the contents of the free-running timer counter registers into the input cap-

ture registers as shown in Figure 9-6.

Latching values into the input capture registers at successive edges of the same

polarity measures the period of the selected input signal. Latching the counter val-

ues at successive edges of opposite polarity measures the pulse width of the sig-

nal.

The input capture registers are made up of two 8-bit read-only registers (ICRH,

ICRL) as shown in Figure 9-9. The input capture edge detector contains a Schmitt

trigger to improve noise immunity. The edge that triggers the counter transfer is

deﬁned by the input edge bit (IEDG) in the TCR. Reset does not affect the con-

tents of the input capture registers.

The result obtained by an input capture will be one count higher than the value of

the free-running timer counter preceding the external transition. This delay is

required for internal synchronization. Resolution is affected by the prescaler,

allowing the free-running timer counter to increment once every four internal clock

cycles (eight oscillator clock cycles).

BIT 7

BIT 6

BIT 5

BIT 4

BIT 3

BIT 2

BIT 1

BIT 0

ICRH

ICRH7

ICRH6

ICRH5

ICRH4

ICRH3

ICRH2

ICRH1

ICRH0

$0014

reset:

UUUUUUUU

ICRL

ICRL7

ICRL6

ICRL5

ICRL4

ICRL3

ICRL2

ICRL1

ICRL0

$0015

reset:

UUUUUUUU

U = UNAFFECTED BY RESET

Figure 9-9. Input Capture Registers (ICRH, ICRL)

VDD ÷ 2

VDD

Output of Comparator

Signal on TCAP pin

Time

Freescale Semiconductor, Inc.

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