PCI6621 datasheet(139/204 Pages) TI

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6−3

6.2

Socket Mask Register

This register allows software to control the CardBus card events which generate a status change interrupt. The state

of these mask bits does not prevent the corresponding bits from reacting in the socket event register (offset 00h, see

Section 6.1). See Table 6−3 for a complete description of the register contents.

Bit

Name

Socket mask

Type

Default

Bit

Name

Socket mask

Type

Default

Socket mask

Offset:

CardBus Socket Address + 04h

Type:

Read-only, Read/Write

Default:

0000 0000h

Table 6−3. Socket Mask Register Description

BIT

SIGNAL

TYPE

FUNCTION

31−4

RSVD

These bits return 0s when read.

3†

PWRMASK

Power cycle. This bit masks the PWRCYCLE bit in the socket present state register (offset 08h, see

Section 6.3) from causing a status change interrupt.

0 = PWRCYCLE event does not cause a CSC interrupt (default).

1 = PWRCYCLE event causes a CSC interrupt.

2−1†

CDMASK

Card detect mask. These bits mask the CDETECT1 and CDETECT2 bits in the socket present state

00 = Insertion/removal does not cause a CSC interrupt (default).

01 = Reserved (undefined)

10 = Reserved (undefined)

11 = Insertion/removal causes a CSC interrupt.

0†

CSTSMASK

CSTSCHG mask. This bit masks the CARDSTS field in the socket present state register (offset 08h, see

Section 6.3) from causing a CSC interrupt.

0 = CARDSTS event does not cause a CSC interrupt (default).

1 = CARDSTS event causes a CSC interrupt.

† This bit is cleared only by the assertion of GRST when PME is enabled. If PME is not enabled, then this bit is cleared by the assertion of PRST

or GRST.

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