PCI6621 datasheet(142/204 Pages) TI

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6−6

Table 6−5. Socket Force Event Register Description

BIT

SIGNAL

TYPE

FUNCTION

31−15

RSVD

Reserved. These bits return 0s when read.

CVSTEST

Card VS test. When this bit is set, the PCI6x21/PCI6x11 controller reinterrogates the PC Card, updates

the socket present state register (offset 08h, see Section 6.3), and re-enables the socket power control.

FYVCARD

Force YV card. Writes to this bit cause the YVCARD bit in the socket present state register (offset 08h,

see Section 6.3) to be written. When set, this bit disables the socket power control.

FXVCARD

Force XV card. Writes to this bit cause the XVCARD bit in the socket present state register (offset 08h,

see Section 6.3) to be written. When set, this bit disables the socket power control.

F3VCARD

Force 3-V card. Writes to this bit cause the 3VCARD bit in the socket present state register (offset 08h,

see Section 6.3) to be written. When set, this bit disables the socket power control.

F5VCARD

Force 5-V card. Writes to this bit cause the 5VCARD bit in the socket present state register (offset 08h,

see Section 6.3) to be written. When set, this bit disables the socket power control.

FBADVCCREQ

Force BadVccReq. Changes to the BADVCCREQ bit in the socket present state register (offset 08h,

see Section 6.3) can be made by writing this bit.

FDATALOST

Force data lost. Writes to this bit cause the DATALOST bit in the socket present state register (offset

08h, see Section 6.3) to be written.

FNOTACARD

Force not a card. Writes to this bit cause the NOTACARD bit in the socket present state register (offset

08h, see Section 6.3) to be written.

RSVD

This bit returns 0 when read.

FCBCARD

Force CardBus card. Writes to this bit cause the CBCARD bit in the socket present state register (offset

08h, see Section 6.3) to be written.

F16BITCARD

Force 16-bit card. Writes to this bit cause the 16BITCARD bit in the socket present state register (offset

08h, see Section 6.3) to be written.

FPWRCYCLE

Force power cycle. Writes to this bit cause the PWREVENT bit in the socket event register (offset 00h,

see Section 6.1) to be written, and the PWRCYCLE bit in the socket present state register (offset 08h,

see Section 6.3) is unaffected.

FCDETECT2

Force CCD2. Writes to this bit cause the CD2EVENT bit in the socket event register (offset 00h, see

Section 6.1) to be written, and the CDETECT2 bit in the socket present state register (offset 08h, see

Section 6.3) is unaffected.

FCDETECT1

Force CCD1. Writes to this bit cause the CD1EVENT bit in the socket event register (offset 00h, see

Section 6.1) to be written, and the CDETECT1 bit in the socket present state register (offset 08h, see

Section 6.3) is unaffected.

FCARDSTS

Force CSTSCHG. Writes to this bit cause the CSTSEVENT bit in the socket event register (offset 00h,

see Section 6.1) to be written. The CARDSTS bit in the socket present state register (offset 08h, see

Section 6.3) is unaffected.

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