PCI6621 datasheet(140/204 Pages) TI

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6−4

6.3

Socket Present State Register

This register reports information about the socket interface. Writes to the socket force event register (offset 0Ch, see

Section 6.4), as well as general socket interface status, are reflected here. Information about PC Card VCC support

and card type is only updated at each insertion. Also note that the PCI6x21/PCI6x11 controller uses the CCD1 and

CCD2 signals during card identification, and changes on these signals during this operation are not reflected in this

Bit

Name

Socket present state

Type

Default

Bit

Name

Socket present state

Type

Default

Socket present state

Offset:

CardBus Socket Address + 08h

Type:

Read-only

Default:

3000 00XXh

Table 6−4. Socket Present State Register Description

BIT

SIGNAL

TYPE

FUNCTION

YVSOCKET

YV socket. This bit indicates whether or not the socket can supply VCC = Y.Y V to PC Cards. The

PCI6x21/PCI6x11 controller does not support Y.Y-V VCC; therefore, this bit is always reset unless

overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.

XVSOCKET

XV socket. This bit indicates whether or not the socket can supply VCC = X.X V to PC Cards. The

PCI6x21/PCI6x11 controller does not support X.X-V VCC; therefore, this bit is always reset unless

overridden by the socket force event register (offset 0Ch, see Section 6.4). This bit defaults to 0.

3VSOCKET

3-V socket. This bit indicates whether or not the socket can supply VCC = 3.3 Vdc to PC Cards. The

PCI6x21/PCI6x11 controller does support 3.3-V VCC; therefore, this bit is always set unless overridden

by the socket force event register (offset 0Ch, see Section 6.4).

5VSOCKET

5-V socket. This bit indicates whether or not the socket can supply VCC = 5 Vdc to PC Cards. The

PCI6x21/PCI6x11 controller does support 5-V VCC; therefore, this bit is always set unless overridden

by bit 6 of the device control register (PCI offset 92h, see Section 4.39).

27−14

RSVD

These bits return 0s when read.

13 †

YVCARD

YV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = Y.Y Vdc.

This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,

see Section 6.4).

12 †

XVCARD

XV card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = X.X Vdc.

This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,

see Section 6.4).

11 †

3VCARD

3-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 3.3 Vdc.

This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,

see Section 6.4).

10 †

5VCARD

5-V card. This bit indicates whether or not the PC Card inserted in the socket supports VCC = 5 Vdc.

This bit can be set by writing a 1 to the corresponding bit in the socket force event register (offset 0Ch,

see Section 6.4).

† One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not

enabled, then these bits are cleared by the assertion of PRST or GRST.

PCI6621 Datasheet(PDF) 140 Page - Texas Instruments

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