PCI6621 datasheet(141/204 Pages) TI

141 / 204 page

6−5

Table 6−4. Socket Present State Register Description (Continued)

BIT

SIGNAL

TYPE

FUNCTION

9 †

BADVCCREQ

Bad VCC request. This bit indicates that the host software has requested that the socket be powered at

an invalid voltage.

0 = Normal operation (default)

1 = Invalid VCC request by host software

8 †

DATALOST

Data lost. This bit indicates that a PC Card removal event may have caused lost data because the cycle

did not terminate properly or because write data still resides in the PCI6x21/PCI6x11 controller.

0 = Normal operation (default)

1 = Potential data loss due to card removal

7 †

NOTACARD

Not a card. This bit indicates that an unrecognizable PC Card has been inserted in the socket. This bit is

not updated until a valid PC Card is inserted into the socket.

0 = Normal operation (default)

1 = Unrecognizable PC Card detected

IREQCINT

READY(IREQ)//CINT. This bit indicates the current status of the READY(IREQ)//CINT signal at the PC

Card interface.

0 = READY(IREQ)//CINT is low.

1 = READY(IREQ)//CINT is high.

5 †

CBCARD

CardBus card detected. This bit indicates that a CardBus PC Card is inserted in the socket. This bit is not

updated until another card interrogation sequence occurs (card insertion).

4 †

16BITCARD

16-bit card detected. This bit indicates that a 16-bit PC Card is inserted in the socket. This bit is not

updated until another card interrogation sequence occurs (card insertion).

3 †

PWRCYCLE

Power cycle. This bit indicates the status of each card powering request. This bit is encoded as:

0 = Socket is powered down (default).

1 = Socket is powered up.

2 †

CDETECT2

CCD2. This bit reflects the current status of the CCD2 signal at the PC Card interface. Changes to this

signal during card interrogation are not reflected here.

0 = CCD2 is low (PC Card may be present)

1 = CCD2 is high (PC Card not present)

1 †

CDETECT1

CCD1. This bit reflects the current status of the CCD1 signal at the PC Card interface. Changes to this

signal during card interrogation are not reflected here.

0 = CCD1 is low (PC Card may be present).

1 = CCD1 is high (PC Card not present).

CARDSTS

CSTSCHG. This bit reflects the current status of the CSTSCHG signal at the PC Card interface.

0 = CSTSCHG is low.

1 = CSTSCHG is high.

† One or more bits in the register are PME context bits and can be cleared only by the assertion of GRST when PME is enabled. If PME is not

enabled, then these bits are cleared by the assertion of PRST or GRST.

6.4

Socket Force Event Register

This register is used to force changes to the socket event register (offset 00h, see Section 6.1) and the socket present

state register (offset 08h, see Section 6.3). The CVSTEST bit (bit 14) in this register must be written when forcing

changes that require card interrogation. See Table 6−5 for a complete description of the register contents.

Bit

Name

Socket force event

Type

Default

Bit

Name

Socket force event

Type

Default

Socket force event

Offset:

CardBus Socket Address + 0Ch

Type:

Read-only, Write-only

Default:

0000 XXXXh

PCI6621 Datasheet(PDF) 141 Page - Texas Instruments

PCI6621 Datasheet(HTML) 141 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL