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PCI6621 Datasheet(PDF) 176 Page - Texas Instruments |
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PCI6621 Datasheet(HTML) 176 Page - Texas Instruments |
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176 / 204 page ![]() 8−16 8.25 Slot 0 3.3-V Maximum Current Register This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field in the slot 0 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a GRST only register. Bit 7 6 5 4 3 2 1 0 Name Slot 0 3.3-V maximum current Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: Slot 3.3-V maximum current Type: Read/Write Offset: 94h Default: 0000h 8.26 Slot 1 3.3-V Maximum Current Register This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field in the slot 1 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a GRST only register. If slot 1 is not implemented, this register is read-only and returns 0s when read. Bit 7 6 5 4 3 2 1 0 Name Slot 1 3.3-V maximum current Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: Slot 1 3.3-V maximum current Type: Read/Write Offset: 98h Default: 0000h 8.27 Slot 2 3.3-V Maximum Current Register This register is a read/write register and the contents of this register are aliased to the 3_3_MAX_CURRENT field in the slot 2 maximum current capabilities register at offset 48h in the SD host standard registers. This register is a GRST only register. If slot 2 is not implemented, this register is read-only and returns 0s when read. Bit 7 6 5 4 3 2 1 0 Name Slot 2 3.3-V maximum current Type RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 Register: Slot 2 3.3-V maximum current Type: Read/Write Offset: 9Ch Default: 0000h |
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