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PCI6621 Datasheet(PDF) 179 Page - Texas Instruments

Part # PCI6621
Description  DUAL/SINGLE SOCKET CARDBUS AND ULTRAMEDIA CONTROLLER
PDF  204 Pages
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Manufacturer  TI [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI - Texas Instruments

PCI6621 Datasheet(HTML) 179 Page - Texas Instruments

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9−1
9 Smart Card Controller Programming Model
This section describes the internal PCI configuration registers used to program the PCI6x21/PCI6x11 Smart Card
controller interface. All registers are detailed in the same format: a brief description for each register is followed by
the register offset and a bit table describing the reset state for each register.
A bit description table, typically included when the register contains bits of more than one type or purpose, indicates
bit field names, a detailed field description, and field access tags which appear in the type column. Table 4−1
describes the field access tags.
The PCI6x21/PCI6x11 controller is a multifunction PCI device. The Smart Card controller core is integrated as PCI
function 5. The function 5 configuration header is compliant with the PCI Local Bus Specification as a standard
header. Table 9−1 illustrates the configuration header that includes both the predefined portion of the configuration
space and the user-definable registers.
Table 9−1. Function 5 Configuration Register Map
REGISTER NAME
OFFSET
Device ID
Vendor ID
00h
Status
Command
04h
Class code
Revision ID
08h
BIST
Header type
Latency timer
Cache line size
0Ch
SC global control base address
10h
SC socket 0 base address
14h
SC socket 1 base address
18h
Reserved
1Ch−28h
Subsystem ID ‡
Subsystem vendor ID ‡
2Ch
Reserved
30h
Reserved
PCI power
management
capabilities pointer
34h
Reserved
38h
Maximum latency
Minimum grant
Interrupt pin
Interrupt line
3Ch
Reserved
40h
Power management capabilities
Next item pointer
Capability ID
44h
PM data
(Reserved)
PMCSR_BSE
Power management control and status ‡
48h
Reserved
General control ‡
4Ch
Subsystem alias
50h
Class code alias
54h
Smart Card configuration 1
58h
Smart Card configuration 2
5Ch
Reserved
60h−FCh
‡ One or more bits in this register are cleared only by the assertion of GRST.



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