PCI6621 datasheet(183/204 Pages) TI

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9−5

9.5

Class Code and Revision ID Register

The class code and revision ID register categorizes the base class, subclass, and programming interface of the

function. The base class is 07h, identifying the controller as a communication device. The subclass is 80h, identifying

the function as other mass storage controller, and the programming interface is 00h. Furthermore, the TI chip revision

is indicated in the least significant byte (00h). See Table 9−4 for a complete description of the register contents.

Bit

Name

Class code and revision ID

Type

Default

Bit

Name

Class code and revision ID

Type

Default

Class code and revision ID

Offset:

08h

Type:

Read-only

Default:

0780 0000h

Table 9−4. Class Code and Revision ID Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

31−24

BASECLASS

Base class. This field returns 07h when read, which classifies the function as a communication device.

23−16

SUBCLASS

Subclass. This field returns 80h when read, which specifically classifies the function as other mass

storage controller.

15−8

PGMIF

Programming interface. This field returns 00h when read.

7−0

CHIPREV

Silicon revision. This field returns 00h when read, which indicates the silicon revision of the Smart Card

controller.

9.6

Latency Timer and Class Cache Line Size Register

The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size

and the latency timer associated with the Smart Card controller. See Table 9−5 for a complete description of the

Bit

Name

Latency timer and class cache line size

Type

Default

Latency timer and class cache line size

Offset:

0Ch

Type:

Read/Write

Default:

0000h

Table 9−5. Latency Timer and Class Cache Line Size Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15−8

LATENCY_TIMER

PCI latency timer. The value in this register specifies the latency timer for the Smart Card controller,

in units of PCI clock cycles. When the Smart Card controller is a PCI bus initiator and asserts FRAME,

the latency timer begins counting from zero. If the latency timer expires before the Smart Card

transaction has terminated, then the Smart Card controller terminates the transaction when its GNT

is deasserted.

7−0

CACHELINE_SZ

Cache line size. This value is used by the Smart Card controller during memory write and invalidate,

memory-read line, and memory-read multiple transactions.

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