PCI6621 datasheet(182/204 Pages) TI

182 / 204 page

9−4

9.4

Status Register

The status register provides device information to the host system. All bit functions adhere to the definitions in the

PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A

bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. See

Table 9−3 for a complete description of the register contents.

Bit

Name

Status

Type

RCU

Default

Status

Offset:

06h

Type:

Read/Clear/Update, Read-only

Default:

0210h

Table 9−3. Status Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

PAR_ERR

RCU

Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.

SYS_ERR

RCU

Signaled system error. Bit 14 is set to 1 when SERR is enabled and the Smart Card controller has

signaled a system error to the host.

MABORT

This function does not support bus mastering. This bit is hardwired to 0.

TABT_REC

This function does not support bus mastering and never receives a target abort. This bit is hardwired

to 0.

TABT_SIG

RCU

Signaled target abort. Bit 11 is set to 1 by the Smart Card controller when it terminates a transaction

on the PCI bus with a target abort.

10−9

PCI_SPEED

DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b, indicating that

the Smart Card controller asserts this signal at a medium speed on nonconfiguration cycle accesses.

DATAPAR

This function does not support bus mastering. This bit is hardwired to 0.

FBB_CAP

Fast back-to-back capable. The Smart Card controller cannot accept fast back-to-back transactions;

therefore, bit 7 is hardwired to 0.

RSVD

Reserved. Bit 6 returns 0 when read.

66MHZ

66-MHz capable. The Smart Card controller operates at a maximum PCLK frequency of 33 MHz;

therefore, bit 5 is hardwired to 0.

CAPLIST

Capabilities list. Bit 4 returns 1 when read, indicating that the Smart Card controller supports additional

PCI capabilities. The linked list of PCI power-management capabilities is implemented in this function.

INT_STAT

Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE)

in the command register (see Section 7.3) is a 0 and this bit is 1, is the function’s INTx signal asserted.

Setting the INT_DISABLE bit to 1 has no effect on the state of this bit. This bit is set only when a valid

interrupt condition exists. This bit is not set when an interrupt condition exists and signaling of that event

is not enabled.

2−0

RSVD

Reserved. Bits 3−0 return 0s when read.

PCI6621 Datasheet(PDF) 182 Page - Texas Instruments

PCI6621 Datasheet(HTML) 182 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68 69 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 87 88 89 90 91 92 93 94 95 96 97 98 99 100 ...More

Datasheet Download

Link URL