PCI6421 datasheet(105/204 Pages) TI

105 / 204 page

4−29

4.40 Diagnostic Register

The diagnostic register is provided for internal TI test purposes. It is a read/write register, but only 0s must be written

to it. See Table 4−18 for a complete description of the register contents.

Bit

Name

Diagnostic

Type

Default

Diagnostic

Offset:

93h (functions 0, 1)

Type:

Read/Write

Default:

60h

Table 4−18. Diagnostic Register Description

BIT

SIGNAL

TYPE

FUNCTION

7 ‡§

TRUE_VAL

This bit defaults to 0. This bit is encoded as:

0 = Reads true values in PCI vendor ID and PCI device ID registers (default)

1 = Returns all 1s to reads from the PCI vendor ID and PCI device ID registers

6 ‡

RSVD

Reserved. This bit is read-only and returns 1 when read.

5 ‡

CSC

CSC interrupt routing control

0 = CSC interrupts routed to PCI if ExCA 803 bit 4 = 1

1 = CSC interrupts routed to PCI if ExCA 805 bits 7−4 = 0000b (default).

In this case, the setting of ExCA 803 bit 4 is a don’t care.

4 ‡§

DIAG4

Diagnostic RETRY_DIS. Delayed transaction disable.

3 ‡§

DIAG3

Diagnostic RETRY_EXT. Extends the latency from 16 to 64.

2 ‡§

DIAG2

Diagnostic DISCARD_TIM_SEL_CB. Set = 210, reset = 215.

1 ‡§

DIAG1

Diagnostic DISCARD_TIM_SEL_PCI. Set = 210, reset = 215.

0 ‡

RSVD

These bits are reserved. Do not change the value of these bits.

‡ One or more bits in this register are cleared only by the assertion of GRST.

§ This bit is global and is accessed only through function 0.

PCI6421 Datasheet(PDF) 105 Page - Texas Instruments

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