PCI6421 datasheet(147/204 Pages) TI

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7−3

7.3

Command Register

The command register provides control over the PCI6x21/PCI6x11 interface to the PCI bus. All bit functions adhere

to the definitions in the PCI Local Bus Specification, as seen in the following bit descriptions. See Table 7−2 for a

complete description of the register contents.

Bit

Name

Command

Type

Default

Command

Offset:

04h

Type:

Read/Write, Read-only

Default:

0000h

Table 7−2. Command Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

15−11

RSVD

Reserved. Bits 15−11 return 0s when read.

INT_DISABLE

INTx disable. When set to 1, this bit disables the function from asserting interrupts on the INTx signals.

0 = INTx assertion is enabled (default)

1 = INTx assertion is disabled

FBB_ENB

Fast back-to-back enable. The flash media interface does not generate fast back-to-back transactions;

therefore, bit 9 returns 0 when read.

SERR_ENB

SERR enable. When bit 8 is set to 1, the flash media interface SERR driver is enabled. SERR can be

asserted after detecting an address parity error on the PCI bus.

STEP_ENB

Address/data stepping control. The flash media interface does not support address/data stepping;

therefore, bit 7 is hardwired to 0.

PERR_ENB

Parity error enable. When bit 6 is set to 1, the flash media interface is enabled to drive PERR response

to parity errors through the PERR signal.

VGA_ENB

VGA palette snoop enable. The flash media interface does not feature VGA palette snooping;

therefore, bit 5 returns 0 when read.

MWI_ENB

Memory write and invalidate enable. The flash media controller does not generate memory write

invalidate transactions; therefore, bit 4 returns 0 when read.

SPECIAL

Special cycle enable. The flash media interface does not respond to special cycle transactions;

therefore, bit 3 returns 0 when read.

MASTER_ENB

Bus master enable. When bit 2 is set to 1, the flash media interface is enabled to initiate cycles on the

PCI bus.

MEMORY_ENB

Memory response enable. Setting bit 1 to 1 enables the flash media interface to respond to memory

cycles on the PCI bus.

IO_ENB

I/O space enable. The flash media interface does not implement any I/O-mapped functionality;

therefore, bit 0 returns 0 when read.

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