PCI6421 datasheet(148/204 Pages) TI

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7−4

7.4

Status Register

The status register provides device information to the host system. All bit functions adhere to the definitions in the

PCI Local Bus Specification, as seen in the following bit descriptions. Bits in this register may be read normally. A

bit in the status register is reset when a 1 is written to that bit location; a 0 written to a bit location has no effect. See

Table 7−3 for a complete description of the register contents.

Bit

Name

Status

Type

RCU

Default

Status

Offset:

06h

Type:

Read/Clear/Update, Read-only

Default:

0210h

Table 7−3. Status Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

PAR_ERR

RCU

Detected parity error. Bit 15 is set to 1 when either an address parity or data parity error is detected.

SYS_ERR

RCU

Signaled system error. Bit 14 is set to 1 when SERR is enabled and the flash media controller has

signaled a system error to the host.

MABORT

RCU

Received master abort. Bit 13 is set to 1 when a cycle initiated by the flash media controller on the PCI

bus has been terminated by a master abort.

TABORT_REC

RCU

Received target abort. Bit 12 is set to 1 when a cycle initiated by the flash media controller on the PCI

bus was terminated by a target abort.

TABORT_SIG

RCU

Signaled target abort. Bit 11 is set to 1 by the flash media controller when it terminates a transaction

on the PCI bus with a target abort.

10−9

PCI_SPEED

DEVSEL timing. Bits 10 and 9 encode the timing of DEVSEL and are hardwired to 01b, indicating that

the flash media controller asserts this signal at a medium speed on nonconfiguration cycle accesses.

DATAPAR

RCU

Data parity error detected. Bit 8 is set to 1 when the following conditions have been met:

a. PERR was asserted by any PCI device including the flash media controller.

b. The flash media controller was the bus master during the data parity error.

c. Bit 6 (PERR_EN) in the command register at offset 04h in the PCI configuration space

(see Section 7.3) is set to 1.

FBB_CAP

Fast back-to-back capable. The flash media controller cannot accept fast back-to-back transactions;

therefore, bit 7 is hardwired to 0.

UDF

User-definable features (UDF) supported. The flash media controller does not support the UDF;

therefore, bit 6 is hardwired to 0.

66MHZ

66-MHz capable. The flash media controller operates at a maximum PCLK frequency of 33 MHz;

therefore, bit 5 is hardwired to 0.

CAPLIST

Capabilities list. Bit 4 returns 1 when read, indicating that the flash media controller supports additional

PCI capabilities.

INT_STATUS

Interrupt status. This bit reflects the interrupt status of the function. Only when bit 10 (INT_DISABLE)

in the command register (see Section 7.3) is a 0 and this bit is 1, is the function’s INTx signal asserted.

Setting the INT_DISABLE bit to 1 has no effect on the state of this bit. This bit is set only when a valid

interrupt condition exists. This bit is not set when an interrupt condition exists and signaling of that event

is not enabled.

2−0

RSVD

Reserved. Bits 3−0 return 0s when read.

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