PCI6421 datasheet(152/204 Pages) TI

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7−8

7.12 Interrupt Line Register

The interrupt line register is programmed by the system and indicates to the software which interrupt line the flash

media interface has assigned to it. The default value of this register is FFh, indicating that an interrupt line has not

yet been assigned to the function.

Bit

Name

Interrupt line

Type

Default

Interrupt line

Offset:

3Ch

Type:

Read/Write

Default:

FFh

7.13 Interrupt Pin Register

This register decodes the interrupt select inputs and returns the proper interrupt value based on Table 7−8, indicating

that the flash media interface uses an interrupt. If one of the USE_INTx terminals is asserted, the interrupt select bits

are ignored, and this register returns the interrupt value for the highest priority USE_INTx terminal that is asserted.

If bit 28, the tie-all bit (TIEALL), in the system control register (PCI offset 80h, see Section 4.29) is set to 1, then the

PCI6x21/PCI6x11 controller asserts the USE_INTA input to the flash media controller core. If bit 28 (TIEALL) in the

system control register (PCI offset 80h, see Section 4.29) is set to 0, then none of the USE_INTx inputs are asserted

and the interrupt for the flash media function is selected by the INT_SEL bits in the flash media general control register.

Bit

Name

Interrupt pin

Type

Default

Interrupt pin

Offset:

3Dh

Type:

Read-only

Default:

0Xh

Table 7−8. PCI Interrupt Pin Register

INT_SEL BITS

USE_INTA

INTPIN

01h (INTA)

02h (INTB)

03h (INTC)

04h (INTD)

01h (INTA)

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