PCI6421 datasheet(153/204 Pages) TI

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7−9

7.14 Minimum Grant Register

The minimum grant register contains the minimum grant value for the flash media controller core.

Bit

Name

Minimum grant

Type

Default

Minimum grant

Offset:

3Eh

Type:

Read/Update

Default:

07h

Table 7−9. Minimum Grant Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

7−0

MIN_GNT

Minimum grant. The contents of this field may be used by host BIOS to assign a latency timer register value

to the flash media controller. The default for this register indicates that the flash media controller may need

to sustain burst transfers for nearly 64

µs and thus request a large value be programmed in bits 15−8 of

the PCI6x21/PCI6x11 latency timer and class cache line size register at offset 0Ch in the PCI configuration

space (see Section 7.6).

7.15 Maximum Latency Register

The maximum latency register contains the maximum latency value for the flash media controller core.

Bit

Name

Maximum latency

Type

Default

Maximum latency

Offset:

3Eh

Type:

Read/Update

Default:

04h

Table 7−10. Maximum Latency Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

7−0

MAX_LAT

Maximum latency. The contents of this field may be used by host BIOS to assign an arbitration priority level

to the flash media controller. The default for this register indicates that the flash media controller may need

to access the PCI bus as often as every 0.25

µs; thus, an extremely high priority level is requested. The

contents of this field may also be loaded through the serial EEPROM.

PCI6421 Datasheet(PDF) 153 Page - Texas Instruments

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