PCI6421 datasheet(155/204 Pages) TI

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7−11

7.17 Power Management Capabilities Register

The power management capabilities register indicates the capabilities of the flash media controller related to PCI

power management. See Table 7−12 for a complete description of the register contents.

Bit

Name

Power management capabilities

Type

Default

Power management capabilities

Offset:

46h

Type:

Read/Update, Read-only

Default:

7E02h

Table 7−12. Power Management Capabilities Register Description

BIT

FIELD NAME

TYPE

DESCRIPTION

PME_D3COLD

PME support from D3cold. This bit can be set to 1 or cleared to 0 via bit 4 (D3_COLD) in the general

control register at offset 4Ch in the PCI configuration space (see Section 7.21). When this bit is set to

1, it indicates that the controller is capable of generating a PME wake event from D3cold. This bit state

is dependent upon the PCI6x21/PCI6x11 VAUX implementation and may be configured by using bit 4

(D3_COLD) in the general control register (see Section 7.21).

14−11

PME_SUPPORT

PME support. This 4-bit field indicates the power states from which the flash media interface may

assert PME. This field returns a value of 1111b by default, indicating that PME may be asserted from

the D3hot, D2, D1, and D0 power states.

D2_SUPPORT

D2 support. Bit 10 is hardwired to 1, indicating that the flash media controller supports the D2 power

state.

D1_SUPPORT

D1 support. Bit 9 is hardwired to 1, indicating that the flash media controller supports the D1 power

state.

8−6

AUX_CURRENT

Auxiliary current. This 3-bit field reports the 3.3-VAUX auxiliary current requirements. When bit 15

(PME_D3COLD) is cleared, this field returns 000b; otherwise, it returns 001b.

000b = Self-powered

001b = 55 mA (3.3-VAUX maximum current required)

DSI

Device-specific initialization. This bit returns 0 when read, indicating that the flash media controller

does not require special initialization beyond the standard PCI configuration header before a generic

class driver is able to use it.

RSVD

Reserved. Bit 4 returns 0 when read.

PME_CLK

PME clock. This bit returns 0 when read, indicating that the PCI clock is not required for the flash media

controller to generate PME.

2−0

PM_VERSION

Power-management version. This field returns 010b when read, indicating that the flash media

controller is compatible with the registers described in the PCI Bus Power Management Interface

Specification (Revision 1.1).

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