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PCI6421 Datasheet(PDF) 150 Page - Texas Instruments |
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PCI6421 Datasheet(HTML) 150 Page - Texas Instruments |
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150 / 204 page  7−6 7.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the flash media controller PCI header type and no built-in self-test. See Table 7−6 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Header type and BIST Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 Register: Header type and BIST Offset: 0Eh Type: Read-only Default: 0010h Table 7−6. Header Type and BIST Register Description BIT FIELD NAME TYPE DESCRIPTION 15−8 BIST R Built-in self-test. The flash media controller does not include a BIST; therefore, this field returns 00h when read. 7−0 HEADER_TYPE R PCI header type. The flash media controller includes the standard PCI header. Bit 7 indicates if the flash media is a multifunction device. 7.8 Flash Media Base Address Register The flash media base address register specifies the base address of the memory-mapped interface registers. Since the implementation of the flash media controller core in the PCI6x21/PCI6x11 controller contains 2 sockets, the size of the base address register is 8192 bytes. See Table 7−7 for a complete description of the register contents. Bit 31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16 Name Flash media base address Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Flash media base address Type RW RW RW RW RW R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Flash media base address Offset: 10h Type: Read/Write, Read-only Default: 0000 0000h Table 7−7. Flash Media Base Address Register Description BIT FIELD NAME TYPE DESCRIPTION 31−12 BAR RW Base address. This field specifies the upper bits of the 32-bit starting base address. 11−4 RSVD R Reserved. Bits 11−4 return 0s when read to indicate that the size of the base address is 8192 bytes. 3 PREFETCHABLE R Prefetchable. Since this base address is not prefetchable, bit 3 returns 0 when read. 2−1 RSVD R Reserved. Bits 2−1 return 0s when read. 0 MEM_INDICATOR R Memory space indicator. Bit 0 is hardwired to 0 to indicate that the base address maps into memory space. |
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