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PCI6421 Datasheet(PDF) 166 Page - Texas Instruments |
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PCI6421 Datasheet(HTML) 166 Page - Texas Instruments |
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166 / 204 page  8−6 8.6 Latency Timer and Class Cache Line Size Register The latency timer and class cache line size register is programmed by host BIOS to indicate system cache line size and the latency timer associated with the SD host controller. See Table 8−5 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Latency timer and class cache line size Type RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW RW Default 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Register: Latency timer and class cache line size Offset: 0Ch Type: Read/Write Default: 0000h Table 8−5. Latency Timer and Class Cache Line Size Register Description BIT FIELD NAME TYPE DESCRIPTION 15−8 LATENCY_TIMER RW PCI latency timer. The value in this register specifies the latency timer for the SD host controller, in units of PCI clock cycles. When the SD host controller is a PCI bus initiator and asserts FRAME, the latency timer begins counting from zero. If the latency timer expires before the SD host transaction has terminated, then the SD host controller terminates the transaction when its GNT is deasserted. 7−0 CACHELINE_SZ RW Cache line size. This value is used by the SD host controller during memory write and invalidate, memory-read line, and memory-read multiple transactions. 8.7 Header Type and BIST Register The header type and built-in self-test (BIST) register indicates the SD host controller PCI header type and no built-in self-test. See Table 8−6 for a complete description of the register contents. Bit 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 Name Header type and BIST Type R R R R R R R R R R R R R R R R Default 0 0 0 0 0 0 0 0 x 0 0 0 0 0 0 0 Register: Header type and BIST Offset: 0Eh Type: Read-only Default: 00x0h Table 8−6. Header Type and BIST Register Description BIT FIELD NAME TYPE DESCRIPTION 15−8 BIST R Built-in self-test. The SD host controller does not include a BIST; therefore, this field returns 00h when read. 7−0 HEADER_TYPE R PCI header type. The SD host controller includes the standard PCI header. Bit 7 indicates if the SD host is a multifunction device. |
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