C8051F310 datasheet(154/224 Pages) ETC1

154 / 224 page

C8051F310/1/2/3/4/5/6/7

154

Rev. 1.6

14.5.2. Master Receiver Mode

Serial data is received on SDA while the serial clock is output on SCL. The SMBus interface generates the

START condition and transmits the first byte containing the address of the target slave and the data direc-

tion bit. In this case the data direction bit (R/W) will be logic 1 (READ). Serial data is then received from the

slave on SDA while the SMBus outputs the serial clock. The slave transmits one or more bytes of serial

data. After each byte is received, ACKRQ is set to ‘1’ and an interrupt is generated. Software must write

the ACK bit (SMB0CN.1) to define the outgoing acknowledge value (Note: writing a ‘1’ to the ACK bit gen-

erates an ACK; writing a ‘0’ generates a NACK). Software should write a ‘0’ to the ACK bit after the last

byte is received, to transmit a NACK. The interface exits Master Receiver Mode after the STO bit is set and

a STOP is generated. Note that the interface will switch to Master Transmitter Mode if SMB0DAT is written

while an active Master Receiver. Figure 14.6 shows a typical Master Receiver sequence. Two received

data bytes are shown, though any number of bytes may be received. Notice that the ‘data byte transferred’

interrupts occur before the ACK cycle in this mode.

Figure 14.6. Typical Master Receiver Sequence

Data Byte

SLA

S = START

P = STOP

A = ACK

N = NACK

R = READ

SLA = Slave Address

Received by SMBus

Interface

Transmitted by

SMBus Interface

Interrupt

C8051F310 Datasheet(PDF) 154 Page - List of Unclassifed Manufacturers