INTELLON CONFIDENTIAL
11
ADVANCE INFORMATION
Rev 8.1
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
MII Data Interface with MDI Control
Data communication between the INT5130 and the external host controller is provided via the Media
Independent Interface or a reduced General Purpose Serial Interface. The MII_GPSI_N select pin is included
on the chip interface to configure the INT5130 in either MII mode or GPSI mode. Access to the INT5130’s
internal MII status and control registers is via the Management Data Interface or a SPI interface. The
MDI_SPIS_N select pin is included on the chip interface to configure the INT5130 in either MDI mode or SPI
mode. The information that follows describes the MII communication interface along with the MDI management
interface as a typical example.
External
Host
Controller
INT5130
MII_RX(3:0)
MII_TX(3:0)
MII_RXCLK
MII_RX_ER
MII_RXDV
MII_CRS
MII_TXCLK
MII_TX_ER
MII_MDCLK
MII_MDIO
MII_COL
MII_TXEN
Figure 2: MII Data Interface with MDI Control
MII Interface
MII is an industry standard, multi-vendor, interoperable interface between separate MAC and PHY devices.
It provides a simple interconnection between the INT5130 and IEEE802.3 Ethernet MAC controllers
(commonly referred to as external host controllers in this document) available from a variety of IC suppliers.
The MII consists of separate 4-bit data paths for transmit and receive data along with carrier sense and
collision detection. Data is transferred between the MAC and PHY over each 4-bit data path synchronous
with a clock signal supplied to the host by the INT5130. The MII interface also provides a two wire bi-
directional serial management data interface (MDI). This interface provides access to the status and
control registers in the INT5130.
MII Timing Diagrams
Figure 3 below shows the transmission behavior of the MII interface. Figure 4 shows the receive
behavior of the MII interface. Figure 5 shows an unsuccessful attempt to transmit a packet, resulting in
a collision.
NOTE: MII_CRS is asynchronous to MII_TXCLK.
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