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INTELLON CONFIDENTIAL
30
ADVANCE INFORMATION
Rev 8.1
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
SPI Master Timing Diagram
t
SPI_HIGH
t
SPI_LOW
DATA
DATA
SPI_SCLK
SPI_DI
SPI_DO
SPI_CS
t
SPI_SU
t
SPI_H
t
SPI_CSL
t
SPI_CSVD
t
SPI_DIVD
Figure 24: SPI Master Signal Timing Diagram
SPI Master DC Characteristics
Parameter
Symbol
Parameter Name
Test Condition
Min
Max
Unit
tSPI_F
SPI_SCLK Frequency
6.125
MHz
tSPI_HIGH
SPI_SCLK High Time
@ 1.5 V
70
90
ns
tSPI_LOW
SPI_SCLK Low Time
@ 1.5 V
70
90
ns
tSPI_DIVD
SPI_DI Valid Output Delay from SPI_SCLK
@ 1.5 V
0
15
ns
tSPI_CSVD
SPI_CS Valid Output Delay from SPI_SCLK
@ 1.5 V
0
15
ns
tSPI_CSL
SPI_CS Low Time
@ 1.5 V
1000
ns
tSPI_SU
SPI_DO Setup Time to SPI_SCLK
@ 1.5 V
50
ns
tSPI_H
SPI_DO Hold Time to SPI_SCLK
@ 1.5 V
0
ns
Table 13: SPI Master DC Characteristics
LEDs
Signal
Status
Description
LED0_N
Collision
LED0_N: Collision Detection
Activate for a duration of 250 ms upon
detection of a collision.
LED1_N
Activity
LED1_N: Activity Detection
Activate for a duration of 250 ms upon the
receipt of a properly addressed unicast or
broadcast frame or the transmission of a
frame.
LED2_N
Link
LED2_N: Link Detection
Turns on when initialization is complete
successfully and “network” is established.
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