INTELLON CONFIDENTIAL
24
ADVANCE INFORMATION
Rev 8.1
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
On transmit, the INT5130 asserts GPSI_TXBSY some time after GPSI_TXEN becomes active, and
drops GPSI_TXBSY after GPSI_TXEN goes inactive AND when the INT5130 is ready to accept
another packet for transmission. When GPSI_TXBSY falls, the external host controller may assert
GPSI_TXEN again if there is another packet to send.
GPSI_TXBSY does not affect nor reflect the receive side of the channel. Once packets start arriving
off of the powerline medium and begin transmission to the external host controller over the GPSI
interface, the external host controller MUST be ready to receive or the packet can be lost.
GPSI_TXEN: GPSI_TXEN from the external host provides the framing for the Ethernet packet. An
active GPSI_TXEN indicates to the INT5130 that data on GPSI_TXD should be sampled using
GPSI_TXCLK.
GPSI_TXD: GPSI_TXD contains the data to be transmitted and transitions synchronously with
respect to GPSI_TXCLK. It is generally assumed that the data will contain a properly formatted
Ethernet frame (see MII Frame Structure above). That is, the first bits on GPSI_TXD correspond to
the preamble, followed by Start Frame Delimiter (SFD) and the rest of the Ethernet frame (DA, SA,
length/type, data, CRC).
SPI Slave Interface
The INT5130 implements a SPI Slave port that when connected to an external host controller containing a
SPI Master, can be used to control access to the two configuration registers. The SPI Slave port uses a
16-bit control field (msb first) consisting of a 6-bit command field, a 5-bit reserved field, and a 5-bit address
field to control access to the two configuration registers detailed above. Following the control field, the 16-
bit register contents are written or read based on the command field.
Control Field
15
14
13
12
11
10
9
8
7
6
5
4
3
2
1
0
Command Field
Reserved Field
Address Field
Register function
5
4
3
2
1
0
4
3
2
1
0
4
3
2
1
0
Write PLCSR0
(Control Register)
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
L
Read PLCSR0
(Control Register)
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
L
Write PLCSR1
(Status Register)
L
L
L
L
H
L
H
L
L
L
L
L
L
L
L
H
Read PLCSR1
(Status Register)
L
L
L
L
H
H
H
L
L
L
L
L
L
L
L
H
Table 7: SPI Slave Command Summary
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