INTELLON CONFIDENTIAL
25
ADVANCE INFORMATION
Rev 8.1
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
SPI SlaveTiming Diagram
t
SPIS_HIGH
SPIS_SCLK
SPIS_SDO
SPIS_SDI
SPIS_CS_N
MSB IN
t
SPIS_LOW
BITS 6-1
LSB IN
MSB OUT
BITS 6-1
LSB OUT
t
SPIS_SU
t
SPIS_H
t
SPIS_CSLEAD
t
SPIS_CSLAG
t
SPIS_SDOVD
Figure 18: SPI Slave Signal Timing
SPI Slave DC Characteristics
Parameter
Symbol
Parameter Name
Test Condition
Min
Max
Unit
tSPIS_F
SPIS_SCLK Frequency
2.1
MHz
tSPIS_HIGH
SPIS_SCLK High Time
@ 1.5 V
400
ns
tSPIS_LOW
SPIS_SCLK Low Time
@ 1.5 V
400
ns
tSPIS_SDOVD
SPIS_SDO Valid Output Delay from SPIS_SCLK
@ 1.5 V
0
500
ns
tSPIS_CSLEAD
SPIS_CS Lead to SPIS_SCLK
@ 1.5 V
500
ns
tSPIS_CSLAG
SPIS_CS Lag from SPIS_SCLK
@ 1.5 V
1500
ns
tSPIS_SU
SPIS_SDI Setup Time to SPIS_SCLK
@ 1.5 V
200
ns
tSPIS_H
SPIS_SDI Hold Time to SPIS_SCLK
@ 1.5 V
200
ns
Table 8: SPI Slave DC Characteristics
Clocks
The INT5130 runs from a single 100MHz oscillator input and generates a 50MHz clock to feed the ADC, a
50MHz clock to feed the DAC, the 25MHz MII clock, and the 10MHz GPSI clock. The 100MHz clock input
directly feeds the clock distribution network that clocks up to 60% of the digital logic. Note: Both CLKIN and
CLKOUT connect directly to the 2.5 V core of the IC and do not connect to the 3.3 V I/O ring. Therefore these
pins are not 3.3V or 5V tolerant.
The oscillator must have
±25 PPM RMS maximum tolerance including initial accuracy, temperature/voltage
range and 5 years of aging. This oscillator must have a symmetry no worse than 40/60, jitter of 75 ps and 4 ns
rise and fall time. The oscillator must be rated over the desired temperature range and
±10% voltage range.
The INT5130 uses a crystal input cell to receive the clock input.
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