INTELLON CONFIDENTIAL
18
ADVANCE INFORMATION
Rev 8.1
INT5130 Integrated Powerline MAC/PHY Transceiver Technical Data Sheet
t
MDI_TH
t
MDI_TSU
MII_MDCLK
MII_MDIO
DATA
Figure 12: MDI Transmit Timing Diagram
MDI DC Characteristics
Parameter
Symbol
Parameter Name
Test Condition
Min
Max
Unit
tMDI_RVAL
MII_MDIO valid from
↑
MII_MDCLK
measured from Vilmax = 0.8V or
measured from Vihmin = 2.0V
0
300
ns
tMDI_TSU
MII_MDIO setup to
↑
MII_MDCLK
measured from Vilmax = 0.8V or
measured from Vihmin = 2.0V
10
ns
tMDI_TH
MII_MDIO hold to
↑
MII_MDCLK
measured from Vilmax = 0.8V or
measured from Vihmin = 2.0V
10
ns
Receive Timing
Transmit Timing
Table 4: MDI DC Characteristics
MDI Signal Descriptions
Management Data Input/Output
MII_MDIO is a bi-directional signal that is used to transfer status and control information between
the INT5130 and the external host. Control information is driven by the external host
synchronously with respect to MII_MDCLK and is sampled synchronously by the INT5130. Status
information is transferred from the INT5130 to the external host in the same manner.
Management Data Clock
MII_MDCLK is sourced by the external host as the timing reference for transfer of information on
the MII_MDIO signal.
MII Management Register Set
The IEEE 802.3u mandated management data registers for control and status are accessible via the
Management Data Interface (MDI). These registers are also accessible via the industry supported serial
peripheral interface. The MDI Port will only respond to addresses 0xbXX000 when the XX field (MSBits of
the MDI address) match the state of the MDI_ADRSEL[1:0] input signals. These registers can also be
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