VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

CCD ANALOG FRONT END

SLES027 – MARCH 2002

7

POST OFFICE BOX 655303

digital specifications

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Logic Inputs

IIH

High-level input current

DVDD = 3 V

–10

10

µA

IIL

Low-level input current

DVDD = 3 V

–10

10

µA

CI

Input capacitance

5

pF

Logic Outputs

VOH

High-level output voltage

IOH= 50 µA, DIVDD = 3 V

DIVDD–0.4

V

VOL

Low-level output voltage

IOL= 50 µA, DIVDD = 3 V

0.4

V

IOZ

High-impedance-state output current

±10

µA

Co

Output capacitance

5

pF

key timing requirement

PARAMETER

TEST CONDITIONS

MIN

TYP

MAX

UNIT

Maximum programming range for SR and ADCCLK timing

signals

T†

ns

SR and ADCCLK programming resolution

T/30

ns

tSRW

SR pulse width

Measured at 50% of pulse

height, recommend to use T/4

of ADCCLK cycle

10

ns

tSRD

Delay between the rising edge of external SR test output

and the actual sampling instant

2.4‡

ns

tADCKD

Delay between the falling edge of external ADCCLK test

output and the actual instant of sampling the video signal

Measured at 50% of pulse

hiht

1.7§

ns

tOD

The rising edge of MCLK to output data delay

height

6

ns

tCSF

CS falling edge to SCLK rising edge

0

ns

tCSR

SCLK falling edge to CS rising edge

5

ns

† T is the time period of MCLK.

‡ SR is the internally generated timing. Due to the pad delay on the output SR, the maximum of the SR delay is 2.4 ns. It must not be delayed further

on the positive direction unless it crosses a full pixel period (refer to Figure 2). The target for the SR position is to make sure that the rising edge

of SR sample the reference level of the CCD signal.

§ ADCCLK is the internally generated timing. Due to the pad delay on the output ADCCLK, the maximum of the ADCCLK delay is 1.7 ns. It must

not be delayed further on the positive direction unless it crosses a full pixel period (refer to Figure 2). The target for the SR position is to make

sure that the falling edge of ADCCLK sample the video level of the active instant of the CCD signal.

NOTE: The digital output is latched out by MCLK.