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VSP10T21 Datasheet(PDF) 18 Page - Texas Instruments |
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VSP10T21 Datasheet(HTML) 18 Page - Texas Instruments |
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18 / 21 page ![]() VSP10T21 3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL CCD ANALOG FRONT END SLES027 – MARCH 2002 18 POST OFFICE BOX 655303 • DALLAS, TEXAS 75265 PRINCIPLES OF OPERATION grounding and decoupling General practices must apply to the printed-circuit board (PCB) design to limit high frequency transients and noise that are fed back into the supply and reference lines. This requires that the supply and reference terminals be sufficiently bypassed. In the case of power supply decoupling, 0.1- µF ceramic chip capacitors are adequate to keep the impedance low over a wide frequency range. Recommended external decoupling for the three voltage reference terminals is shown in Figure 4. Since the effectiveness of the decoupling capacitors depends largely on the proximity to the individual supply terminal, all decoupling capacitors must be placed as close as possible to the supply terminals. An inductor is recommended for the DIVDD power supply (see Figure 4). Common ground is also recommended. voltage references An internal precision voltage reference of 1.5 V nominal is provided. This reference voltage generates the ADC Ref– voltage of 1 V and Ref+ of 2 V. It also sets the clamp voltage. All internally generated voltages are fixed values and cannot be adjusted. Terminals 37 (RBD), 38 (RPD), and 39 (RMD) must not be used to drive any loads. |
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