VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

CCD ANALOG FRONT END

SLES027 – MARCH 2002

16

POST OFFICE BOX 655303

PRINCIPLES OF OPERATION

internal timing

As previously explained, the SR and ADCCLK clocks are required to operate the CDS. Users need to

synchronize the SR and ADCCLK clocks with the CCD signal waveform. The output from the ADC is read out

to external circuitry by the MCLK signal that is the external signal used to generate the SR and ADCCLK clocks

internally. The user can use the SR and ADCCLK internal delay register to program the delay of these clocks

based on Figure 2 in order to achieve the optimal performance. Terminals 21 (SR) and 22 (ADCCLK) are used

to monitor these two internal signals. By changing bit D2 (CKIP) in the clock control register, the AFE digital

output is latched at either the rising edge or the falling edge of the MCLK pulse.

The CLAMP signal activates the clamping circuit for the input signal. The OBCLP signal activates the optical

black calibration and the active portion (the low pulse) of this signal must be within the optical black period of

the CCD (see Figure 1).

ADC

The ADC employs a pipelined architecture to achieve high throughput and low power consumption. Fully

differential implementation and digital error correction ensure 10-bit resolution.

The latency of the ADC data output is the default 5 MCLK cycles as shown in Figure 2. Pulling terminal 42 (OE)

high puts the ADC output in high impedance.

automatic optical black calibration

In the VSP10T21 device, the optical black and the system channel offset corrections are performed by an auto

analog feedback loop. During the optical black calibration interval (OBCLP = low) of each line, the optical black

pixels plus the channel offset are sampled and compared with the desired black level specified in the optical

black Vb setup register. The difference is then integrated and added to incoming pixel data at PGA input. This

analog feedback loop calibrates the PGA output to the desired black pixel level, which can be programmed

either to 0 or from 20 LSB to 35 LSB at 1 LSB/step resolution typically via the serial port. The OB calibration

settles within about 1000 OB pixels.

input blanking function

During blanking period of CCD operation, large input transients may occur at the VSP10T21 device’s input,

making the ADC output unpredictable. Activating BLKG pulse during this period ensures the digital code is zero

at the ADC output.

user DACs

The VSP10T21 device includes two user DACs that can be used for external analog settings. These are resistor

string DACs. They must be used only to drive capacitor or buffer loads, not resistor loads. The output voltage

of each DAC can be independently set and has a range of 0 V to the supply voltage with 8-bit resolution. When

the user DACs are not used in a camera system, they can be put in the standby mode by programming control

bits in the control register 1. The status of the user DACs is defined in the following table.