VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

CCD ANALOG FRONT END

SLES027 – MARCH 2002

11

POST OFFICE BOX 655303

REGISTER DEFINITION

serial input data format

DI15

DI14

DI13

DI12

DI11

DI10

DI9

DI8

DI7

DI6

DI5

DI4

DI3

DI2

DI1

DI0

X

X

A3

A2

A1

A0

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

A3

A2

A1

A0

D9–D10

0000

Control register

10-bit data to be written into the selected register

0001

PGA gain register

0010

User DAC1 register

0011

User DAC2 register

0100

Reserved

0101

Optical black Vb setup register

0110

Video control register

0111

Reserved

1000

SR and ADC delay register

1001

Clock control register

control register format (00H)

D9

D8

D7

D6

D5

D4

D3

D2

D1

D0

STBY

PDD1

PDD2

DACD

x

x

x

x

x

RTSY

control register description

BIT

NAME

DESCRIPTION

D9

STBY

Device power down control

1 = Standby

0 = Active (default)

D8

PDD1

Power down the user DAC1

1 = Standby

0 = Active (default)

D7

PDD2

Power down the user DAC2

1 = Standby

0 = Active (default)

D6

DACD

Sustain the user DACs when power down

0 = User DACs are powered down during global power-down (default)

1 = User DACs are not powered down during global power-down

D5

x

Reserved

D4

x

Reserved

D3

x

Reserved

D2

x

Reserved

D1

x

Reserved

D0

RTSY

Writing a 1 to this bit will reset entire system to the default settings (active high).

Default = 00 0000 0000