VSP10T21

3-V, 10-BIT, 21-MSPS, ENHANCED TIMING CONTROL

CCD ANALOG FRONT END

SLES027 – MARCH 2002

3

POST OFFICE BOX 655303

functional block diagram

1.2 V Ref

CDS

DIN+

DIN–

PIN

Clamp

Video

Clamp

CLAMP CLREF

AVDD (4 PLACES)

Internal

Reference

RBD

RPD

RMD

PGA

Optical

Black

Loop

10

PGA

Register

DVDD

DIVDD

10-Bit

ADC

Three-State

Latch

Timing

and

Control

Logic

BLKG

OBCLP

STBY

D0

D9

Thru

Serial

Port

CS

SCLK

SCKP

SDIN

OE

8-Bit

DAC

DAC2

Reg

DACO2

8-Bit

DAC

DAC1

Reg

DACO1

AVSS (4 PLACES)

DVSS

DIVSS

VSS

MCLK

RESET

ADCCLK†

SR†

DLL

† ADCCLK and SR output signals are only enabled by setting bits D3 (ADEN) and D4 (ROEN) in the clock control register to 1.