845GL datasheet(78/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.2

Host-to-AGP Bridge Registers (Device 1)

The host-to-AGP Bridge (virtual PCI-to-PCI) registers are in Device 1. This section contains the

PCI configuration registers listed in order of ascending offset address. Table 3-3 provides the

Table 3-3. Host-to-AGP Register Address Map (Device 1)

Address

Offset

Symbol

Default Value

Access

00–01h

VID1

Vendor Identification

8086h

02–03h

DID1

Device Identification

2561h

04–05h

PCICMD1

PCI Command

0000h

RO, R/W

06–07h

PCISTS1

PCI Status

00A0h

RO, R/WC

08h

RID1

Revision Identification

see register

description

09h

—

Intel Reserved

—

0Ah

SUBC1

Sub-Class Code

04h

0Bh

BCC1

Base Class Code

06h

0Ch

—

Intel Reserved

—

0Dh

MLT1

Master Latency Timer

00h

RO, R/W

0Eh

HDR1

Header Type

01h

0F–17h

—

Intel Reserved

—

18h

PBUSN1

Primary Bus Number

00h

19h

SBUSN1

Secondary Bus Number

00h

R/W

1Ah

SUBUSN1

Subordinate Bus Number

00h

R/W

1Bh

SMLT1

Secondary Bus Master Latency Timer

00h

RO, R/W

1Ch

IOBASE1

I/O Base Address

F0h

RO, R/W

1Dh

IOLIMIT1

I/O Limit Address

00h

RO, R/W

1E–1Fh

SSTS1

Secondary Status

02A0h

RO, R/WC

20–21h

MBASE1

Memory Base Address

FFF0h

RO, R/W

22–23h

MLIMIT1

Memory Limit Address

0000h

RO, R/W

24–25h

PMBASE1

Prefetchable Memory Base Limit

Address

FFF0h

RO, R/W

26–27h

PMLIMIT1

Prefetchable Memory Limit Address

0000h

RO, R/W

28–3Dh

—

Intel Reserved

—

3Eh

BCTRL1

Bridge Control

00h

RO, R/W

40h

ERRCMD1

Error Command

00h

RO, R/W

41–FFh

—

Intel Reserved

—

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