845GL datasheet(90/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

3.5.2.21

BCTRL1—Bridge Control Register (Device 1)

Address Offset:

3Eh

Default Value:

00h

Access:

RO, R/W

Size:

8 bits

This register provides extensions to the PCICMD1 register that are specific to PCI-to-PCI bridges.

The BCTRL1 provides additional control for the secondary interface (i.e., PCI_B/AGP) as well as

some bits that affect the overall behavior of the “virtual” PCI-to-PCI bridge embedded within the

GMCH (e.g., VGA compatible address ranges mapping).

Bit

Description

Fast Back-to-Back Enable (FB2BEN)—RO.

Hardwired to 0. The GMCH does not generate fast

back-to-back cycles as a master on AGP.

Secondary Bus Reset (SRESET)—RO.

Hardwired to 0. GMCH does not support generation of

reset via this bit on the AGP.

Master Abort Mode (MAMODE)—RO.

Hardwired to 0. This means when acting as a master on

AGP/PCI_B the GMCH will drop writes on the floor and return all ones during reads when a Master

Abort occurs.

Reserved.

VGA Enable (VGAEN)—R/W.

This bit controls the routing of processor-initiated transactions

targeting VGA compatible I/O and memory address ranges.

0 = Disable.

1 = Enable.

ISA Enable (ISAEN)—R/W.

This bit modifies the response by the GMCH to an I/O access issued by

the processor that targets ISA I/O addresses. This applies only to I/O addresses that are enabled by

the IOBASE and IOLIMIT registers.

0 = Disable (default). All addresses defined by the IOBASE and IOLIMIT for processor I/O

transactions are mapped to PCI_B/AGP.

1 = Enable. GMCH does Not forward to PCI_B/AGP any I/O transactions addressing the last

768 bytes in each 1 KB block, even if the addresses are within the range defined by the IOBASE

and IOLIMIT registers. Instead of going to PCI_B/AGP these cycles will be forwarded to the hub

interface where they can be subtractively or positively claimed by the ISA bridge.

SERR Enable (SERREN)—RO.

Hardwired to 0. This bit normally controls forwarding SERR# on the

secondary interface to the primary interface. The GMCH does not support the SERR# signal on the

AGP/PCI_B bus.

Parity Error Response Enable (PEREN)—R/W.

This bit controls GMCH’s response to data phase

parity errors on PCI_B/AGP. G_PERR# is not implemented by the GMCH.

0 = Disable. Address and data parity errors on PCI_B/AGP are not reported via the GMCH HI SERR

messaging mechanism. Other types of error conditions can still be signaled via SERR

messaging independent of this bit’s state.

1 = Enable. Address and data parity errors detected on PCI_B are reported via the HI SERR

messaging mechanism, if further enabled by SERRE1.

845GL Datasheet(PDF) 90 Page - Intel Corporation

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