845GL datasheet(130/193 Pages) INTEL

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Functional Description

130

Intel® 82845G/82845GL/82845GV GMCH Datasheet

Dynamic Bob and Weave

Interlaced data that originates from a video camera creates two fields that are temporally offset by

1/60 of a second. There are several schemes to deinterlace the video stream: line replication,

vertical filtering, field merging, and vertical temporal filtering. Field merging takes lines from the

previous field and inserts them into the current field to construct the frame – this is known as

Weaving. This is the best solution for images with little motion; however; showing a frame that

consists of the two fields will have serration or feathering of moving edges when there is motion in

the scene. Vertical filtering or “Bob” interpolates adjacent lines rather replicating the nearest

neighbor. This is the best solution for images with motion; however, it will have reduced spatial

resolution in areas that have no motion and introduces “jaggies.” In absence of any other

deinterlacing, these form the baseline and are supported by the GMCH.

Scaling Filter and Control

The scaling filter has 2-vertical taps and 5-horizontal taps. Arbitrary scaling (per pixel granularity)

for any video source format is supported.

The overlay logic can scale an input image up to 1600x1200 with no major degradation in the filter

used as long as the maximum frequency limitation is met. Display resolution and refresh rate

combinations where the dot clock is greater than the maximum frequency require the overlay to use

pixel replication.

4.4.3

Pipes

The display consists of a single pipe. The pipe can operate in a single-wide or double-wide mode at

2X graphics core clock; however, it is effectively limited by its display port (350 MHz max). The

primary display plane and the cursor plane provides a “double wide” mode to feed the pipe.

4.4.3.1

Clock Generator Units (DPLL)

The clock generator units provide a stable frequency for driving display devices. It operates by

converting an input reference frequency into an output frequency. The timing generators take their

input from the internal DPLL device that is programmable to generate pixel clocks in the range of

25 MHz –350 MHz. Accuracy for VESA timing modes is required to be within

± 0.5%.

The DPLL can take a reference frequency from the external reference input (DREFCLK) or the TV

clock input (DVOBC_CLKINT).

4.4.4

Ports

For more information on ports, refer to Section 4.5.

845GL Datasheet(PDF) 130 Page - Intel Corporation