845GL datasheet(139/193 Pages) INTEL

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Intel® 82845G/82845GL/82845GV GMCH Datasheet

139

System Address

An mPGA478 processor system based on the GMCH supports 4 GB of addressable memory space

and 64 KB+3 of addressable I/O space. There is a programmable memory address space under the

1-MB region that is divided into regions which can be individually controlled with programmable

attributes (e.g., disable, read/write, write only, or read only). Attribute programming is described in

Chapter 3. This section focuses on how the memory space is partitioned and what the separate

memory regions are used for. I/O address space has simpler mapping and is explained at the end of

this section.

The mPGA478 processor family supports addressing of memory ranges larger than 4 GB. The

GMCH claims any processor access over 4 GB and terminates the transaction without forwarding

it to the hub interface or AGP. Simply dropping the data terminates writes. For reads, the GMCH

returns all zeros on the host bus. Note that the 845G chipset does not support the PCI Dual Address

Cycle Mechanism; therefore, the GMCH does not allow addressing of greater than 4 GB on either

the hub interface or AGP interface.

In the following sections, it is assumed that all of the compatibility memory ranges reside on the

hub interface/PCI. The exception to this rule is VGA ranges, which may be mapped to AGP or to

the IGD. In the absence of more specific references, cycle descriptions referencing PCI should be

interpreted as the hub interface/PCI, while cycle descriptions referencing AGP are related to the

AGP bus. The 845G chipset memory address map includes a number of programmable ranges.

Warning: All of these ranges must be unique and non-overlapping. There are no hardware interlocks to

prevent problems in the case of overlapping ranges. Accesses to overlapped ranges may produce

indeterminate results.

5.1

System Memory Address Ranges

The GMCH provides a maximum SDRAM address decode space of 2 GB. The GMCH does not

remap APIC memory space. The GMCH does not limit SDRAM space in hardware.

Note: It is the BIOS or system designers’ responsibility to limit memory population so that adequate PCI,

AGP, High BIOS, and APIC memory space can be allocated.

Figure 5-1 shows the system memory address map in a simplified form. Figure 5-2 provides

additional details on mapping specific memory regions as defined and supported by the GMCH.

845GL Datasheet(PDF) 139 Page - Intel Corporation