RT8152C datasheet(16/24 Pages) RICHTEK

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RT8152C/D

DS8152C/D-04

April 2011

www.richtek.com

Considering the inductance tolerance, the resistor RX has

to be tuned on board by examining the transient voltage.

If the output voltage transient has an initial dip below the

minimum load line requirement with a slow recovery, RX

is chosen too small. Vice versa, with a resistance too

large, the output voltage transient has only a small initial

dip and the recovery is too fast causing a ring-back.

Using current sense resistor in series with the inductor

can have better accuracy, but the efficiency is a trade-off.

Considering the equivalent inductance (LESL) of the current

sense resistor, a RC filter is recommended. The RC filter

calculation method is similar to the above mentioned

inductor DCR sensing method.

Loop Control

The RT8152C/D adopts Richtek's proprietary G-NAVPTM

topology. G-NAVPTM is based on the finite-gain current

mode with CCRCOT (Constant Current Ripple Constant

On Time) topology. The output voltage, VOUT, will decrease

with increasing output load current. The control loop

consists of PWM modulator with power stage, current

sense amplifier and error amplifier as shown in Figure 4.

Figure 4. Simplified Schematic for Droop and Remote

Sense in CCM

The HS_FET on-time is determined by CCRCOT ON-Time

generator. When load current increases, VCS increases,

the steady state COMP voltage also increases and makes

the VOUT decrease, achieving AVP. A near-DC offset

cancellation is added to the output of EA to cancel the

inherent output offset of finite-gain current mode controller.

In RFM, HS_FET is turned on with constant TON when

VCS is lower than VCOMP2. Once the HS_FET is turned off,

LS_FET is turned on automatically. By Ringing-Free

Technique, the LS_FET allows only partial of negative

current when the inductor free-wheeling current reaches

negative. The switching frequency will be proportionately

reduced, thus the conduction and switching losses will

be greatly reduced.

Output Voltage Droop Setting (with Temperature

Compensation)

It's very easy to achieve the Active Voltage Positioning

(AVP) by properly setting the error amplifier gain due to

the native droop characteristics. The target is to have

VOUT = VDAC

− ILOAD x RDROOP

(3)

, then solving the switching condition VCOMP2 = VCS in

Figure 4 yields the desired error amplifier gain as

SENSE

DROOP

(4)

where AI is the internal current sense amplifier gain. RSENSE

is the current sense resistor. If no external sense resistor

present, it is the DCR of the inductor. RDROOP is the

resistive slope value of the converter output and is the

desired static output impedance.

Figure 5. Error Amplifier Gain (Av) Influence on VOUT

AV1

AV2

AV2 > AV1

VOUT

Load Current

VOUT

CCRCOT

PWM

Logic

UGATE

LGATE

ISEN

ISEN_N

CMP

VCS

COMP2

VIN

RT8152C/D

HS_FET

LS_FET

VCC_SENSE

VSS_SENSE

SOFT

RGND

COMP

CSOFT

VDAC

Offset

Cancellation

RT8152C Datasheet(PDF) 16 Page - Richtek Technology Corporation

RT8152C Datasheet(HTML) 16 Page - Richtek Technology Corporation

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