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RT8152C Datasheet(PDF) 19 Page - Richtek Technology Corporation |
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RT8152C Datasheet(HTML) 19 Page - Richtek Technology Corporation |
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19 / 24 page ![]() RT8152C/D 19 DS8152C/D-04 April 2011 www.richtek.com Figure 8. CPU Mode Timing Diagram for Power-Up and Power-Down After the RT8152C/D enters Render mode, VSEN starts ramping up to VDAC within 1ms. The slew rate during power-up is 20 μA/CSOFT. PGOOD is asserted HIGH after VSEN exceeds VDAC − 100mV for 4.77ms (typ.). DPRSLPVR are valid right after PGOOD is asserted. UVP is masked as long as VSEN is less than VDAC − 100mV. Figure 9. Render Mode Timing Diagram for Power-Up and Power-Down VRON VCC 4.3V 4.1V VID Valid xx XX VSEN PGOOD 4.77ms typ. POR 0.2V VDAC VDAC-100mV DPRSLPVR Valid XX XX PWM DPRSLPVR Defined CCM Pull Down CCM Hi-Z VRON VCC 4.3V 4.1V VID Valid xx XX VSEN PGOOD 73µs typ. 4.7ms typ. POR 0.2V VBOOT VBOOT - 0.1V DPRSLPVR Valid XX XX PWM DPRSLPVR Defined CCM Pull Down CCM Hi-Z CLKEN |
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