RT8152C datasheet(23/24 Pages) RICHTEK

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RT8152C/D

DS8152C/D-04

April 2011

www.richtek.com

close proximity to the load. Latter ones are for mid-

frequency decoupling with especially small ESR and ESL

values while the bulk capacitors have to provide enough

stored energy to overcome the low frequency bandwidth

gap between the regulator and the CPU.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature. The maximum

power dissipation depends on the thermal resistance of

IC package, PCB layout, the rate of surroundings airflow

and temperature difference between junction to ambient.

The maximum power dissipation can be calculated by

following formula :

PD(MAX) = (TJ(MAX)

− TA) / θJA

Where TJ(MAX) is the maximum operation junction

temperature, TA is the ambient temperature and the

θJAis

the junction to ambient thermal resistance.

For recommended operating conditions specification of

RT8152C/D, The maximum junction temperature is 125

°C.

The junction to ambient thermal resistance

θJA is layout

dependent. For WQFN-32L 5x5 package, the thermal

resistance

θJA is 36°C/W on the standard JEDEC 51-7

four layers thermal test board. The maximum power

dissipation at TA = 25

°C can be calculated by following

formula :

PD(MAX) = (12

°C − 25°C) / (36°C/W) = 2.778W for

WQFN-32L 5x5 package

The maximum power dissipation depends on operating

ambient temperature for fixed TJ(MAX) and thermal

resistance

θJA. For RT8152C/D package, the Figure 15 of

derating curve allows the designer to see the effect of

rising ambient temperature on the maximum power

allowed.

Layout Considerations

Careful PC board layout is critical to achieve low switching

losses and clean, stable operation. The switching power

stage requires particular attention. If possible, mount all

of the power components on the top side of the board

with their ground terminals flush against one another.

Follow these guidelines for optimum PC board layout :

Keep the high current paths short, especially at the

ground terminals.

Keep the power traces and load connections short. This

is essential for high efficiency.

The slew rate control capacitor should be connected

from SOFT to RGND, and it should be placed physically

close to IC.

Connect slew rate control capacitor at SOFT pin to

RGND.

When trade-offs in trace lengths must be made, it’s

preferable to allow the inductor charging path to be made

longer than the discharging path.

Place the current sense component close to the

controller. ISEN and ISEN_N connections for current limit

and voltage positioning must be made using Kelvin sense

connections to guarantee the current sense accuracy.

The PCB trace from the sense nodes should be parallel

back to controller.

Route high speed switching nodes away from sensitive

analog areas (SOFT, COMP, FB, VSEN, ISEN, ISEN_N,

CM, etc...)

Figure 15. Derating Curve for RT8152C/D Package

0.0

0.2

0.4

0.6

0.8

1.0

1.2

1.4

1.6

1.8

2.0

2.2

2.4

2.6

2.8

3.0

100

125

Ambient Temperature (°C)

Four Layers PCB

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