RT8152C datasheet(17/24 Pages) RICHTEK

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RT8152C/D

DS8152C/D-04

April 2011

www.richtek.com

Since the DCR of inductor is highly temperature dependent,

it affects the output accuracy at hot conditions.

Temperature compensation is recommended for the

lossless inductor DCR current sense method. Figure 6

shows a simple but effective way of compensating the

temperature variations of the sense resistor using an NTC

thermistor placed in the feedback path.

Figure 6. Loop Setting with Temperature Compensation

Usually, R1a is set to equal RNTC (25oC). R1b is selected

to linearize the NTC's temperature characteristic. For a

given NTC, design is to get R1b and R2 and then C1 and

C2. According to (4), to compensate the temperature

variations of the sense resistor, the error amplifier gain

(Av) should have the same temperature coefficient with

RSENSE. Hence

V, HOT

SENSE, HOT

V, COLD

SENSE, COLD

(5)

From (4), we can have Av at any temperature (T) as

V, T

NTC, T

R1a // R

R1b

(6)

(

) ( )

{

}

T+273

298

NTC, T

NTC, 25

⎡⎤

β−

⎢⎥

⎣⎦

(7)

The standard formula for the resistance of NTC thermistor

as a function of temperature is given by :

Where RNTC, 25 is the thermistor's nominal resistance at

room temperature,

β (beta) is the thermistor's material

constant in Kelvins, and T is the thermistor's actual

temperature in Celsius.

To calculate DCR value at different temperature can use

equation as below :

DCRT = DCR25 x [1+0.00393 x (T

−25)]

(8)

Where the 0.00393 is the temperature coefficient of the

copper. For a given NTC thermistor, solving (6) at room

temperature (25

°C) yields :

R2 = AV, 25 x (R1b + R1a // RNTC, 25)

(9)

Where AV, 25 is the error amplifier gain at room temperature

and can be obtained from (4). R1b can be obtained by

substituting (9) to (5),

SENSE, HOT

NTC, HOT

NTC, COLD

SENSE, COLD

SENSE, HOT

SENSE, COLD

R1b

(R1a // R

) (R1a // R

)

×−

⎛⎞

−

⎜⎟

⎝⎠

(10)

Loop Compensation

Optimized compensation of the RT8152C/D allows for best

possible load step response of the regulator's output. A

compensator with one pole and one zero is adequate for

a proper compensation. Figure 4 shows the compensation

circuit. Prior design procedure shows how to decide the

resistive feedback components of error amplifier gain, the

C1 and C2 must be calculated for the compensation. The

target is to achieve the constant resistive output impedance

over the widest possible frequency range.

The pole frequency of the compensator must be set to

compensate the output capacitor ESR zero :

2C R

×π × ×

(11)

Where C is the capacitance of output capacitor, and RC is

the ESR of output capacitor. C2 can be calculated as

follows :

(12)

(13)

()

NTC, 25

R1b R1a // R

+× π ×

The zero of compensator has to be placed at half of the

switching frequency to filter the switching related noise.

Such that :

TON Setting

High frequency operation optimizes the application for the

smaller component size, trading off efficiency due to higher

switching losses. This may be acceptable in ultra portable

devices where the load currents are lower and the

controller is powered from a lower voltage supply. Low

frequency operation offers the best overall efficiency at

the expense of component size and board space. Figure

VCC_SENSE

VSS_SENSE

SOFT

RGND

COMP

RT8152C/D

R1b

CSOFT

10nF

R1a

NTC

VDAC

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