PC8245 datasheet(13/61 Pages) ATMEL

13 / 61 page

PC8245

2171D–HIREL–06/04

Figure 2 shows supply voltage sequencing and separation cautions.

Figure 2. Supply Voltage Sequencing and Separation Cautions

Notes:

1. Numbers associated with waveform separations correspond to caution numbers listed in Table “Recommended Operating

Conditions” on page 12.

2. Refer to section for additional information.

3. Refer to Table 7 on page 25 for additional information on PLL Relock and reset signal assertion timing requirements.

4. Refer to Table 9 on page 31 for additional information on reset configuration pin setup timing requirements.

5. HRST_CPU/HRST_CTRL must transition from a logic 0 to a logic 1 in less than one SDRAM_SYNC_IN clock cycle for the

device to be in the non-reset state.

GVdd_OVdd/(LVdd at 3.3V ----)

Vdd/AVdd/AVdd2

LVdd at 5V

Time

3.3V

2.0V

6.8

Voltage

Regulator

Delay(2)

Reset

Configuration Pins

HRST_CPU &

HRST_CTRL

asserted 255

external memory

Clock cycles(3)

9 external memory

clock cycles setup time(4)

HRST_CPU,

HRST_CTRL

Vdd Stable

See Note (1)

VM = 1.4V

Maximum rise time must be less than

one external memory clock cycle(5)

100

µs

PLL

Relock

Time(3)

Power Supply Ramp Up(2)

PC8245 Datasheet(PDF) 13 Page - ATMEL Corporation

PC8245 Datasheet(HTML) 13 Page - ATMEL Corporation

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