USB3450 datasheet(26/40 Pages) SMSC

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Hi-Speed USB Host or Device PHY With UTMI+ Interface

Datasheet

Revision 0.1 (05-11-05)

SMSC USB3450

DATASHEET

6.4.3

Bias Generator

This block consists of an internal bandgap reference circuit used for generating the high speed driver

currents and the biasing of the analog circuits. This block requires an external 12K

Ω, 1% tolerance,

external reference resistor connected from RBIAS to ground.

6.5

Crystal Oscillator and PLL

The USB3450 uses an internal crystal driver and PLL sub-system to provide a clean 480MHz reference

clock that is used by the PHY during both transmit and receive. The USB3450 requires a clean 24MHz

crystal or clock as a frequency reference. If the 24MHz reference is noisy or off frequency the PHY

may not operate correctly.

The USB3450 can use either a crystal or an external clock oscillator for the 24MHz reference. The

crystal is connected to the XI and XO pins as shown in the application diagram, Figure 7.9. If a clock

oscillator is used the clock should be connected to the XI input and the XO pin left floating. When an

external clock is used the XI pin is designed to be driven with a 0 to 3.3 volt signal. When using an

external clock the user needs to take care to ensure the external clock source is clean enough to not

degrade the high speed eye performance.

Once, the 480MHz PLL has locked to the correct frequency it will drive the CLKOUT pin with a 60MHz

clock. The USB3450 is guaranteed to start the clock within the time specified in Table 5.2.

6.6

Internal Regulators and POR

The USB3450 includes an integrated set of built in power management functions. These power

management features include a POR generation and allow the USB3450 to be powered from a single

3.3 volt power supply. This reduces the bill of materials and simplifies product design.

6.6.1

Internal Regulators

The USB3450 has two internal regulators that create two 1.8V outputs (labeled VDD1.8 and VDDA1.8)

from the 3.3volt power supply input (VDD3.3). Each regulator requires an external 4.7uF +/-20% low

ESR bypass capacitor to ensure stability. X5R or X7R ceramic capacitors are recommended since they

exhibit an ESR lower that 0.1ohm at frequencies greater than 10kHz..

The specific capacitor recommendations for each pin are detailed in Table 3.1, “USB3450 Pin

Definitions,” on page 11, and shown in Figure 7.9 USB3450 Application Diagram (Top View) on

page 39.

Note: The USB3450 regulators are designed to generate a 1.8 volt supply for the USB3450 only.

Using the regulators to provide current for other circuits is not recommended and SMSC does

not guarantee USB performance or regulator stability.

6.6.2

Power On Reset (POR)

The USB3450 provides an internal POR circuit that generates a reset pulse once the PHY supplies

are stable. The UTMI+ Digital can be reset at any time with the RESET pin.

USB3450 Datasheet(PDF) 26 Page - SMSC Corporation

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