M263 datasheet(8/398 Pages) NUVOTON

8 / 398 page

M261/M262/M263

Mar 25, 2020

Page 8 of 398

Rev 1.02

LIST OF FIGURES

Figure 4.1-1 M261 Series QFN 33-pin Diagram ............................................................................ 28

Figure 4.1-2 M261 Series LQFP 64-pin Diagram .......................................................................... 29

Figure 4.1-3 M261 Series LQFP 128-pin Diagram ........................................................................ 30

Figure 4.1-4 M262 Series QFN 33-pin Diagram ............................................................................ 31

Figure 4.1-5 M262 Series LQFP 64-pin Diagram .......................................................................... 32

Figure 4.1-6 M262 Series LQFP 128-pin Diagram ........................................................................ 33

Figure 4.1-7 M263 Series QFN 33-pin Diagram ............................................................................ 34

Figure 4.1-8 M263 Series LQFP 64-pin Diagram .......................................................................... 35

Figure 4.1-9 M263 Series LQFP 128-pin Diagram ........................................................................ 36

Figure 5.1-1 M261/M262/M263 Series Block Diagram ................................................................ 265

Figure 6.1-1 Cortex

® -M23 Block Diagram.................................................................................... 266

Figure 6.2-1 System Reset Sources ............................................................................................ 269

Figure 6.2-2 nRESET Reset Waveform ....................................................................................... 271

Figure 6.2-3 Power-on Reset (POR) Waveform .......................................................................... 271

Figure 6.2-4 Low Voltage Reset (LVR) Waveform....................................................................... 272

Figure 6.2-5 Brown-out Detector (BOD) Waveform ..................................................................... 273

Figure 6.2-6 Power Mode State Machine .................................................................................... 275

Figure 6.2-7 Power Distribution Diagram ..................................................................................... 279

Figure 6.2-8 SRAM Block Diagram .............................................................................................. 283

Figure 6.2-9 SRAM Memory Organization ................................................................................... 284

Figure 6.2-10 SRAM Marco Organization .................................................................................... 285

Figure 6.3-1 Clock Generator Global View Diagram (1/3) ........................................................... 293

Figure 6.3-2 Clock Generator Global View Diagram (2/3) ........................................................... 294

Figure 6.3-3 Clock Generator Global View Diagram (3/3) ........................................................... 295

Figure 6.3-4 Clock Generator Block Diagram .............................................................................. 296

Figure 6.3-5 System Clock Block Diagram .................................................................................. 297

Figure 6.3-6 HXT Stop Protect Procedure ................................................................................... 298

Figure 6.3-7 SysTick Clock Control Block Diagram ..................................................................... 298

Figure 6.3-8 Clock Output Block Diagram ................................................................................... 299

Figure 6.24-1 SPI Master Mode Application Block Diagram........................................................ 323

Figure 6.24-2 SPI Slave Mode Application Block Diagram.......................................................... 323

Figure 6.25-1 I

2C Bus Timing....................................................................................................... 325

Figure 8.4-1 Typical Crystal Application Circuit ........................................................................... 364

Figure 8.4-2 Typical Crystal Application Circuit ........................................................................... 366

Figure 8.5-1 Power-up Ramp Condition ...................................................................................... 373

Figure 8.5-2 Typical Connection with Internal Voltage Reference............................................... 374

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