M263 datasheet(19/398 Pages) NUVOTON

19 / 398 page

M261/M262/M263

Mar 25, 2020

Page 19 of 398

Rev 1.02

QSPI

 One set of SPI Quad controller with Master/Slave mode

 SPI can communicate at up to 64 Mbit/s

 2-bit Transfer mode

 Dual and Quad I/O Transfer mode

 QSPI provides separate 8-level of 32-bit transmit and receive FIFO

buffers

 Configurable bit length of a transfer word from 8 to 32-bit

 MSB first or LSB first transfer sequence

 Byte reorder function

 Supports Byte or Word Suspend mode

 3-wired, no slave select signal, bi-direction interface

 Supports one data channel half-duplex transfer

 Supports receive-only mode

 PDMA operation

 One set of I

2S interface with Master/Slave mode

 I

2S audio sampling frequencies up to 192 kHz are supported

 Supports mono and stereo audio data with 8-, 16-, 24- and 32-bit

word sizes

 Two 16-level FIFO data buffers, one for transmitting and the other

for receiving

 Supports I

2S protocols: Philips standard, MSB-justified, and LSB-

justified data format

 Supports PCM protocols: PCM standard, MSB-justified, and LSB-

justified data format

 PCM protocol supports TDM multi-channel transmission in one

audio sample; the number of data channel can be set as 2, 4, 6 or 8

 PDMA operation

Universal Serial Control Interface

(USCI)

 Two sets of USCI,configured as UART, SPI or I

2C function

 Supports single byte TX and RX buffer mode

UART

 Supports one transmit buffer and two receive buffers for data

payload

 Supports hardware auto flow control function and programmable

flow control trigger level

 9-bit Data Transfer

 Baud rate detection by built-in capture event of baud rate generator

 Supports wake-up function

 PDMA operation

SPI

 Supports Master or Slave mode operation

 Supports one transmit buffer and two receive buffer for data payload

 Configurable bit length of a transfer word from 4 to 16-bit

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