M263 datasheet(20/398 Pages) NUVOTON

20 / 398 page

M261/M262/M263

Mar 25, 2020

Page 20 of 398

Rev 1.02

 Supports MSB first or LSB first transfer sequence

 Supports Word Suspend function

 Supports 3-wire, no slave select signal, bi-direction interface

 Supports wake-up function by slave select signal in slave mode

 Supports one data channel half-duplex transfer

 PDMA operation

 Supports master and slave device capability

 Supports one transmit buffer and two receive buffer for data payload

 Communication in standard mode (100 kbps), fast mode (up to 400

kbps), and Fast mode plus (1 Mbps)

 Supports 10-bit mode

 Supports 10-bit bus time out capability

 Supports bus monitor mode

 Supports power-down wake-up by data toggle or address match

 Supports multiple address recognition

 Supports device address flag

 Programmable setup/hold time

Controller Area Network (CAN)

 One set of CAN 2.0B controller

 Each supports 32 Message Objects; each Message Object has its

own identifier mask

 Programmable FIFO mode (concatenation of Message Object)

 Disabled Automatic Re-transmission mode for Time Triggered CAN

applications

 Supports power-down wake-up function

Secure Digital Host Controller

(SDHC)

 One set of Secure Digital Host Controller, compliant with SD

Memory Card Specification Version 2.0

 Supports 50 MHz to achieve 200 Mbps at 3.3V operation

 Supports dedicated DMA master with Scatter-Gather function to

accelerate the data transfer between system memory and

SD/SDHC/SDIO card

External Bus Interface (EBI)

 Supports up to three memory banks with individual adjustment of

timing parameter

 Each bank supports dedicated external chip select pin with polarity

control and up to 1 MB addressing space

 8-/16-bit data width

 Supports byte write in 16-bit data width mode

 Supports variable external bus base clock (MCLK) which based on

HCLK

 Configurable idle cycle for different access condition: Idle of Write

command finish (W2X) and Idle of Read-to-Read (R2R)

 Supports Address/Data multiplexed mode

 Supports address bus and data bus separate mode

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