M263 datasheet(18/398 Pages) NUVOTON

18 / 398 page

M261/M262/M263

Mar 25, 2020

Page 18 of 398

Rev 1.02

 PDMA operation

Smart Card Interface

 Three sets of ISO-7816-3 which are compliant with ISO-7816-3 T=0,

T=1

 Supports full duplex UART function

 4-byte FIFOs with programmable level trigger

 Programmable guard time selection (11 ETU ~ 266 ETU)

 One 24-bit and two 8 bit time-out counters for Answer to Request

(ATR) and waiting times processing

 Auto inverse convention function

 Stop clock level and clock stop (clock keep) function

 Transmitter and receiver error retry function

 Supports hardware activation, deactivation and warm reset

sequence process

 Supports hardware auto deactivation sequence after card removal

 Three sets of I

2C devices with Master/Slave mode

 Supports Standard mode (100 kbps), Fast mode (400 kbps) and

Fast mode plus (1 Mbps)

 Supports 10 bits mode

 Programmable clocks allowing for versatile rate control

 Supports multiple address recognition (four slave address with

mask option)

 Supports SMBus and PMBus

 Supports multi-address power-down wake-up function

 PDMA operation

SPI/I

 Up to four sets of SPI/I

2S controllers with Master/Slave mode

 SPI can communicate at up to 64 Mbit/s

 SPI/I

2S provides separate 4-level of 32-bit (or 8-level of 16-bit)

transmit and receive FIFO buffers

SPI

 Configurable bit length of a transfer word from 8 to 32-bit

 MSB first or LSB first transfer sequence

 Byte reorder function

 Supports Byte or Word Suspend mode

 Supports one data channel half-duplex transfer

 Supports receive-only mode

 PDMA operation

 Supports mono and stereo audio data with 8-, 16-, 24- and 32-bit

audio data sizes

 Supports PCM mode A, PCM mode B, I

2S and MSB justified data

format

 PDMA operation

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