ADC3541 datasheet(23/68 Pages) TI1

23 / 68 page

7.3.2 Clock Input

In order to maximize the ADC SNR performance, the external sampling clock should be low jitter and differential

signaling with a high slew rate. This is especially important in IF sampling applications. For less jitter sensitive

applications, the ADC354x provides the option to operate with single ended signaling which saves additional

power consumption.

7.3.2.1 Single Ended vs Differential Clock Input

The ADC354x can be operated using a differential or a single ended clock input where the single ended clock

consumes less power consumption. However clock amplitude impacts the ADC aperture jitter and consequently

the SNR. For maximum SNR performance, a large clock signal with fast slew rates needs to be provided.

• Differential Clock Input: The clock input can be AC coupled externally. The ADC354x provides internal biasing

for that use case.

• Single Ended Clock Input: This mode needs to be configured using SPI register (0x0E, D2 and D0) or with

the REFBUF pin. In this mode there is no internal clock biasing and thus the clock input needs to be DC

coupled around a 0.9V center.

VCM

0.9V

CLKP

CLKM

5kO

CLKP

CLKM

0.9V

1.8V

Figure 7-12. External and internal connection using differential (left) and single ended (right) clock input

7.3.2.2 Signal Acquisition Time Adjust

The ADC354x includes a register (DLL PDN (0x11, D2) which increases the signal acquisition time window for

clock rates below 40 MSPS from 25% to 50% of the clock period. Increasing the sampling time provides a longer

time for the driving amplifier to settle out the signal which can improve the SNR performance of the system.

Note

This register needs to be set for the 65 MSPS speed grade (ADC3543) when operating at sampling

rates below 40 MSPS. For the 10 and 25 MSPS device speed grades the sampling time is already set

to TS/2.

When powering down the DLL, the acquisition time will track the clock duty cycle (50% is recommended).

Table 7-1. Acquisition time vs DLL PDN setting

SAMPLING CLOCK FS (MSPS)

DLL PDN (0x11, D2)

ACQUISITION TIME (tACQ)

TS / 4

≤ 40

TS / 2

www.ti.com

ADC3541

SBAS840 – JULY 2020

Submit Document Feedback

Product Folder Links: ADC3541

ADC3541 Datasheet(PDF) 23 Page - Texas Instruments

ADC3541 Datasheet(HTML) 23 Page - Texas Instruments

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68

Datasheet Download

Link URL