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ADC3541 Datasheet(PDF) 54 Page - Texas Instruments

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Part # ADC3541
Description  ADC354x 14-bit, 10-MSPS to 65-MSPS, Low-noise, Ultra-low Power ADC
PDF  68 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3541 Datasheet(HTML) 54 Page - Texas Instruments

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Figure 7-57. Register 0x1F
7
6
5
4
3
2
1
0
LOW DR EN
DCLKIN EN
0
DCLK OB EN
2X DCLK
0
0
0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-35. Register 0x1F Field Descriptions
Bit
Field
Type
Reset
Description
7
LOW DR EN
R/W
0
This bit impacts the output drive strength of the CMOS output
buffers. This bit can be enabled at slow speeds in order to save
power consumption but it will also degrade the rise and fall
times.
0: Low drive strength disabled.
1: Low drive strength enabled.
6
DCLKIN EN
R/W
0
This bit enables the DCLKIN clock input buffer for serial CMOS
modes. Also DCLKIN EN (0x18, D4) needs to be set as well.
0: DCLKIN buffer powered down.
1: DCLKIN buffer enabled.
5
0
R/W
0
Must write 0
4
DCLK OB EN
R/W
1
This bit enables DCLK output buffer.
0: DCLK output buffer powered down.
1: DCLK output buffer enabled.
3
2X DCLK
R/W
0
This bit enables SDR output clocking with serial CMOS mode.
When this mode is enabled, DCLKIN required is twice as fast
and data is output only on rising edge of DCLK.
0: Normal operation with data output on DCLK rising and falling
edge.
1: 2x DCLK mode enabled with data output on DCLK rising edge
only.
2-0
0
R/W
0
Must write 0
Figure 7-58. Register 0x20/21/22
7
6
5
4
3
2
1
0
FCLK PAT [7:0]
FCLK PAT [15:8]
SCR EN
0
0
FCLK PAT [19:16]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-36. Register 0x20/21/22 Field Descriptions
Bit
Field
Type
Reset
Description
7-0
FCLK PAT [19:0]
R/W
0xFFC00
These bits can adjust the duty cycle of the FCLK. In decimation
bypass mode the FCLK pattern gets adjusted automatically for
the different output resolutions. Table 7-37 shows the proper
FCLK pattern values for 1-wire in real/complex decimation.
7-6
SCR EN
R/W
00
Enables scrambling of the output data
00: no scrambling
01: Scrambling enabled with first polynomial
10: Scrambling enabled with second polynomial
11: 8b/10b encoding
ADC3541
SBAS840 – JULY 2020
www.ti.com
54
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Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: ADC3541



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