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ADC3541 Datasheet(PDF) 46 Page - Texas Instruments

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Part # ADC3541
Description  ADC354x 14-bit, 10-MSPS to 65-MSPS, Low-noise, Ultra-low Power ADC
PDF  68 Pages
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Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3541 Datasheet(HTML) 46 Page - Texas Instruments

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Figure 7-45. Register 0x0A/B/C
7
6
5
4
3
2
1
0
CMOS OB DIS [23:0]
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-19. Register 0x0A/B/C Field Descriptions
Bit
Field
Type
Reset
Description
7:0
CMOS OB DIS [23:0]
R/W
0
These register bits power down the individual CMOS output
buffers. See Table 7-20 for the actual bit to pin mapping. Unused
pins should be powered down (ie set to 1) for maximum power
savings.
There is a separate control to enable the DCLKIN buffer in
register 0x1F (D6) and 0x18 (D4). DCLK output buffer is
powered down using register 0x1F (D4).
NOTE: When using serial CMOS interface the CMOS output
buffer (D3/DB1) has to be powered down because it shares the
pin with DCLKIN.
0: Output buffer enabled
1: Output buffer powered down
Table 7-20. Output buffer enable bit mapping vs output interface mode
ADDRESS (HEX)
BIT
PIN NAME
SDR CMOS
DDR CMOS
SCMOS 2-w
SCMOS 1-w
0x0A
D7
D7
D7
D7
-
-
D6
-
-
-
-
-
D5
-
-
-
-
-
D4
D4
D4
-
-
-
D3
D3
D3
-
DCLKIN
DCLKIN
D2
D2
D2
-
-
-
D1
D1
D1
-
-
-
D0
D0
D0
-
-
-
Register setting
0x60
0x7F
0xFF
0xFF
0x0B
D7
D13
D13
-
-
-
D6
D14
D14
-
-
-
D5
D15
D15
-
-
-
D4
FCLK
-
-
FCLK
FCLK
D3
-
-
-
-
-
D2
-
-
-
-
-
D1
-
-
-
-
-
D0
D8
D8
D8
-
-
Register setting
0x1E
0xFE
0xEF
0xEF
0x0C
D7
D10
D10
D10
-
-
D6
D9
D9
D9
-
-
D5
D6
D6
D6
-
-
D4
D5
D5
D5
-
-
D3
-
-
-
-
-
D2
-
-
-
-
-
D1
D11
D11
D11
D11
D11
D0
D12
D12
D12
D12
-
Register setting
0x0C
0x0C
0xFC
0xFD
ADC3541
SBAS840 – JULY 2020
www.ti.com
46
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Product Folder Links: ADC3541



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