Electronic Components Datasheet Search
  English  ▼

X  

Preview PDF HTML

ADC3541 Datasheet(PDF) 50 Page - Texas Instruments

Click here to check the latest version.
Part # ADC3541
Description  ADC354x 14-bit, 10-MSPS to 65-MSPS, Low-noise, Ultra-low Power ADC
PDF  68 Pages
Scroll/Zoom Zoom In 100%  Zoom Out
Manufacturer  TI1 [Texas Instruments]
Direct Link  http://www.ti.com
Logo TI1 - Texas Instruments

ADC3541 Datasheet(HTML) 50 Page - Texas Instruments

Back Button ADC3541 Datasheet HTML 46Page - Texas Instruments ADC3541 Datasheet HTML 47Page - Texas Instruments ADC3541 Datasheet HTML 48Page - Texas Instruments ADC3541 Datasheet HTML 49Page - Texas Instruments ADC3541 Datasheet HTML 50Page - Texas Instruments ADC3541 Datasheet HTML 51Page - Texas Instruments ADC3541 Datasheet HTML 52Page - Texas Instruments ADC3541 Datasheet HTML 53Page - Texas Instruments ADC3541 Datasheet HTML 54Page - Texas Instruments Next Button
Zoom Inzoom in Zoom Outzoom out
 50 / 68 page
background image
Figure 7-50. Register 0x11
7
6
5
4
3
2
1
0
0
0
SE A
0
0
DLL PDN
0
AZ EN
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-26. Register 0x11 Field Descriptions
Bit
Field
Type
Reset
Description
7-6
0
R/W
0
Must write 0
5
SE A
R/W
0
This bit enables single ended analog input, channel A. In this
mode the SNR reduces by 3-dB.
0: Differential input
1: Single ended input.
4-3
0
R/W
0
Must write 0
2
DLL PDN
R/W
0
This register applies ONLY to the ADC3543. It powers down the
internal DLL, which is used to adjust the sampling time. This
register must be enabled when operating at sampling rates
below 40 MSPS. When DLL PDN bit is enabled the sampling
time is directly dependent on sampling clock duty cycle (with a
50/50 duty the sampling time is TS/2).
0: Sampling time is TS/ 4
1: Sampling time is TS/2 (only for sampling rates below 40
MSPS).
1
0
R/W
0
Must write 0
0
AZ EN
R/W
0/1
This bit enables the internal auto-zero circuitry. It is enabled by
default for the ADC3541/42 and disabled for the ADC3543.
0: Auto-zero disabled
1: Auto-zero enabled
Figure 7-51. Register 0x13
7
6
5
4
3
2
1
0
0
0
0
0
0
0
E-FUSE LD
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
R/W-0
Table 7-27. Register 0x13 Field Descriptions
Bit
Field
Type
Reset
Description
7-1
0
R/W
0
Must write 0
0
E-FUSE LD
R/W
0
This register bit loads the internal bit mapping for different
interfaces. After setting the interface in register 0x07, this E-
FUSE LD bit needs to be set to 1 and reset to 0 for loading to go
into effect. Register 0x07 along with the E-Fuse Load (0x12, D0)
needs to be loaded first in the programming sequence since the
E-Fuse load resets the SPI writes.
0: E-FUSE LOAD set
1: E-FUSE LOAD reset
ADC3541
SBAS840 – JULY 2020
www.ti.com
50
Submit Document Feedback
Copyright © 2020 Texas Instruments Incorporated
Product Folder Links: ADC3541



Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 51 52 53 54 55 56 57 58 59 60 61 62 63 64 65 66 67 68


Datasheet Download

Go To PDF Page


Link URL



Does ALLDATASHEET help your business so far?  [ DONATE ] 

About Alldatasheet   |   Advertisement   |   Contact us   |   Privacy Policy   |   Link to Datasheet    |   Link Exchange   |   Manufacturer List
All Rights Reserved©Alldatasheet.com


Mirror Sites
English : Alldatasheet.com  |   English : Alldatasheet.net  |   Chinese : Alldatasheetcn.com  |   German : Alldatasheetde.com  |   Japanese : Alldatasheet.jp
Russian : Alldatasheetru.com  |   Korean : Alldatasheet.co.kr  |   Spanish : Alldatasheet.es  |   French : Alldatasheet.fr  |   Italian : Alldatasheetit.com
Portuguese : Alldatasheetpt.com  |   Polish : Alldatasheet.pl  |   Vietnamese : Alldatasheet.vn
Indian : Alldatasheet.in  |   Mexican : Alldatasheet.com.mx  |   British : Alldatasheet.co.uk  |   New Zealand : Alldatasheet.co.nz
Family Site : ic2ic.com  |   icmetro.com