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ADC3541 Datasheet(PDF) 45 Page - Texas Instruments |
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ADC3541 Datasheet(HTML) 45 Page - Texas Instruments |
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45 / 68 page  Figure 7-43. Register 0x07 7 6 5 4 3 2 1 0 OP IF MAPPER 0 OP IF EN OP IF SEL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-17. Register 0x07 Field Descriptions Bit Field Type Reset Description 7-5 OP IF MAPPER R/W 000 This register contains the proper output interface bit mapping for the different interfaces. The interface bit mapping is internally loaded from e-fuses and also requires a fuse load command to go into effect (0x13, D0). Register 0x07 along with the E-Fuse Load (0x13, D0) needs to be loaded first in the programming sequence since the E-Fuse load resets the SPI writes. After initial reset the default output interface variant is loaded automatically from fuse internally. However when reading back this register reads 000 until a value is written using SPI. 001: 2-wire, 18 and 14-bit 010: 2-wire, 16-bit 011: 1-wire 100: 0.5-wire 101: DDR 110: SDR 4 0 R/W 0 Must write 0 3 OP IF EN R/W 0 Enables changing the default output interface mode (D2-D0). 2-0 OP IF SEL R/W 000 Selects the output interface mode. OP IF EN (D3) needs to be enabled also.After initial reset the default output interface is loaded automatically from fuse internally. However when reading back this register reads 000 until a value is written using SPI. 000: SDR CMOS 001: DDR CMOS 011: 2-wire 100: 1-wire 101: 0.5-wire others: not used Figure 7-44. Register 0x08 7 6 5 4 3 2 1 0 0 0 PDN CLKBUF PDN REFAMP TEMPS EN PDN A 1 PDN GLOBAL R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 R/W-0 Table 7-18. Register 0x08 Field Descriptions Bit Field Type Reset Description 7-6 0 R/W 0 Must write 0 5 PDN CLKBUF R/W 0 Powers down sampling clock buffer 0: Clock buffer enabled 1: Clock buffer powered down 4 PDN REFAMP R/W 0 Powers down internal reference gain amplifier 0: REFAMP enabled 1: REFAMP powered down 3 TEMPS EN R/W 0 Enables temperature sensor 0: Temperature sensor powered down 1: Temperature sensor enabled 2 PDN A R/W 0 Powers down ADC channel A 0: ADC channel A enabled 1: ADC channel A powered down 1 1 R/W 1 Must write 1 0 PDN GLOBAL R/W 0 Global power down via SPI 0: Global power disabled 1: Global power down enabled. Power down mask (register 0x0D) determines which internal blocks are powered down. www.ti.com ADC3541 SBAS840 – JULY 2020 Copyright © 2020 Texas Instruments Incorporated Submit Document Feedback 45 Product Folder Links: ADC3541 |
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